# Chapter 3: Arithmetic for Computers

Chia sẻ: Phung Chi Kien | Ngày: | Loại File: PDF | Số trang:50

0
68
lượt xem
9

## Chapter 3: Arithmetic for Computers

Mô tả tài liệu

Arithmetic for Computers: Operations on integers: Addition and subtraction, Multiplication and division, Dealing with overflow. Floating-point real numbers: Representation and operations.

Chủ đề:

Bình luận(0)

Lưu

## Nội dung Text: Chapter 3: Arithmetic for Computers

1. dce 2009 KIẾN TRÚC MÁY TÍNH CS2009 Khoa Khoa học và Kỹ thuật Máy tính BK BM Kỹ thuật Máy tính TP.HCM Võ Tấn Phương http://www.cse.hcmut.edu.vn/ vtphuong/KTMT http://www.cse.hcmut.edu.vn/~vtphuong/KTMT
2. dce 2009 Chapter 3 Arithmetic for Computers Adapted from Computer Organization and Design, 4th Edition, Patterson & Hennessy, © 2008 10/18/2009 ©2009, CE Department 2
3. dce 2009 The Five classic Components of a Computer 10/18/2009 ©2009, CE Department 3
4. dce 2009 Arithmetic for Computers • Operations on integers – Addition and subtraction – Multiplication and division – Dealing with overflow • Floating-point real numbers – Representation and operations 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 4
5. dce 2009 Integer Addition • Example: 7 + 6 • Overflow if result out of range – Adding +ve and –ve operands, no overflow – Adding two +ve operands ve • Overflow if result sign is 1 – Adding two –ve operands • Overflow if result sign is 0 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 5
6. dce 2009 Integer Subtraction • Add negation of second operand • Example: 7 – 6 = 7 + (–6) ( 6) +7: 0000 0000 … 0000 0111 –6: 1111 1111 … 1111 1010 +1: 0000 0000 … 0000 0001 • Overflow if result out of range – Subtracting two +ve or two –ve operands, no overflow – Subtracting +ve from –ve operand • Overflow if result sign is 0 – Subtracting –ve from +ve operand • Overflow if result sign is 1 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 6
7. dce 2009 Dealing with Overflow • Some languages (e.g., C) ignore overflow – Use MIPS addu, addui, subu instructions • Other languages (e.g., Ada, Fortran) require raising an exception – Use MIPS add, addi, sub instructions – On overflow, invoke e cep o handler O o e o , o e exception a d e • Save PC in exception program counter (EPC) register •JJump t predefined h dl address to d fi d handler dd • mfc0 (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 7
8. dce 2009 Arithmetic for Multimedia • Graphics and media processing operates on vectors of 8-bit and 16-bit data – Use 64-bit adder, with partitioned carry chain • Operate on 8×8-bit 4×16-bit or 2×32-bit vectors 8×8-bit, 4×16-bit, – SIMD (single-instruction, multiple-data) • Saturating operations – On overflow, result is largest representable value • c.f. 2s-complement modulo arithmetic – E g clipping in audio saturation in video E.g., audio, 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 8
9. dce 2009 Multiplication • Start with long-multiplication approach multiplicand 1000 multiplier × 1001 1000 0000 0000 1000 product 1001000 Length of product is the sum of operand lengths 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 9
10. dce 2009 Multiplication Hardware Initially 0 y 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 10
11. dce 2009 Optimized Multiplier • Perform steps in parallel: add/shift • One cycle per partial-product addition – That’s ok, if frequency of multiplications is low That s ok 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 11
12. dce 2009 Faster Multiplier • Uses multiple adders – Cost/performance tradeoff • Can be pipelined –S Several multiplication performed i parallel l lti li ti f d in ll l 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 12
13. dce 2009 MIPS Multiplication • Two 32-bit registers for product – HI: most-significant 32 bits most significant – LO: least-significant 32-bits • Instructions – mult rs, rt / multu rs, rt • 64-bit product in HI/LO – mfhi rd f / mflo rd f • Move from HI/LO to rd • Can test HI value to see if product overflows 32 bits – mul rd, rs, rt • Least-significant 32 bits of product –> rd 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 13
14. dce 2009 Division • Check for 0 divisor • Long division approach quotient ti t – If divisor ≤ dividend bits dividend • 1 bit in quotient, subtract 1001 – Otherwise 1000 1001010 • 0 bit in quotient, bring down next -1000 dividend bit divisor 10 • Restoring division 101 – Do the subtract, and if remainder 1010 goes < 0, add divisor back -1000 • Signed division remainder i d 10 – Divide using absolute values – Adjust sign of quotient and remainder n-bit operands yield n-bit as required quotient and remainder 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 14
15. dce 2009 Division Hardware Initially divisor in left half Initially dividend 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 15
16. dce 2009 Optimized Divider • One cycle per partial remainder subtraction partial-remainder • Looks a lot like a multiplier! – Same hardware can be used for both 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 16
17. dce 2009 Faster Division • Can’t use parallel hardware as in multiplier – Subtraction is conditional on sign of remainder • Faster dividers (e g SRT devision) (e.g. generate multiple quotient bits per step – Still require m ltiple steps req ire multiple 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 17
18. dce 2009 MIPS Division • Use HI/LO registers for result – HI: 32-bit remainder 32 bit – LO: 32-bit quotient • I t ti Instructions – div rs, rt / divu rs, rt – No overflow or divide-by-0 checking • Software must perform checks if required – Use mfhi, mflo to access result fhi fl 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 18
19. dce 2009 Floating Point • Representation for non-integral numbers – Including very small and very large numbers • Like scientific notation – –2.34 × 1056 2 34 normalized – +0.002 × 10–4 not normalized – +987.02 × 109 • In binary – ±1.xxxxxxx2 × 2yyyy • Types float and double in C ypes oat a d doub e 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 19
20. dce 2009 Floating Point Standard • Defined by IEEE Std 754-1985 • Developed in response to divergence of representations – P t bilit i Portability issues f scientific code for i tifi d • Now almost universally adopted • Two representations – Single p g precision ((32-bit) ) – Double precision (64-bit) 10/18/2009 ©2009, CE Department Chapter 3 — Arithmetic for Computer — 20