Chapter 3: The Processor

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Chapter 3: The Processor

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Introduction: CPU performance factors: Instruction count: Determined by ISA and compiler. CPI and Cycle time: Determined by CPU hardware. We will examine two MIPS implementations: A simplified version, A more realistic pipelined version. Simple subset, shows most aspects: Memory reference: lw, sw, Arithmetic/logical: add, sub, and, or, slt.

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  1. dce 2009 KIẾN TRÚC MÁY TÍNH CS2009 Khoa Khoa học và Kỹ thuật Máy tính BK BM Kỹ thuật Máy tính TP.HCM Võ Tấn Phương http://www.cse.hcmut.edu.vn/ vtphuong/KTMT http://www.cse.hcmut.edu.vn/~vtphuong/KTMT ©2009, CE Department
  2. dce 2009 Chapter 3 The Processor Adapted from Computer Organization and Design, 4th Edition, Patterson & Hennessy, © 2008 11/17/2009 ©2009, CE Department 2
  3. dce 2009 The Five classic Components of a Computer 11/17/2009 ©2009, CE Department 3
  4. dce 2009 Introduction • CPU performance factors – Instruction count • Determined by ISA and compiler – CPI and Cycle time • Determined by CPU hardware • We will examine two MIPS implementations – A simplified version – A more realistic pipelined version • Simple subset, shows most aspects –MMemory reference: l sw f lw, – Arithmetic/logical: add, sub, and, or, slt – Control transfer: beq, j ©2009, CE Department
  5. dce 2009 Instruction Execution • PC → instruction memory, fetch instruction • Register numbers → register file read registers file, • Depending on instruction class – Use ALU to calculate • Arithmetic result • Memory address for load/store • Branch target address – Access data memory for load/store – PC ← target address or PC + 4 ©2009, CE Department
  6. dce 2009 CPU Overview ©2009, CE Department
  7. dce 2009 Multiplexers • Can’t just join wires together – Use multiplexers ©2009, CE Department
  8. dce 2009 Control ©2009, CE Department
  9. dce 2009 Logic Design Basics • Information encoded in binary – Low voltage = 0 High voltage = 1 0, – One wire per bit – Multi bit data encoded on multi wire buses Multi-bit multi-wire • Combinational element – Operate on data – Output is a function of input • State (sequential) elements – Store information ©2009, CE Department
  10. dce 2009 Combinational Elements • AND-gate • Adder A Y + –Y=A&B –Y=A+B B A Y B • Arithmetic/Logic Unit • Multiplexer – Y = F(A, B) – Y = S ? I1 : I0 A I0 M u Y ALU Y I1 x B S F ©2009, CE Department
  11. dce 2009 Sequential Elements • Register: stores data in a circuit – Uses a clock signal to determine when to update the stored value – Edge-triggered: update when Clk changes from 0 to 1 Clk D Q D Clk Q ©2009, CE Department
  12. dce 2009 Sequential Elements • Register with write control – Only updates on clock edge when write control input is 1 – Used when stored value is required later Clk D Q Write Write D Clk Q ©2009, CE Department
  13. dce 2009 Clocking Methodology • Combinational logic transforms data du g c oc cyc es during clock cycles – Between clock edges – Input from state elements, output to state p , p element – Longest delay determines clock period ©2009, CE Department
  14. dce 2009 Building a Datapath • Datapath – Elements that process data and addresses in the CPU • Registers, ALUs, mux’s, memories, … mux s, • We will build a MIPS datapath incrementally – Refining the overview design ©2009, CE Department
  15. dce 2009 Instruction Fetch Increment by 4 for next 32-bit instruction register ©2009, CE Department
  16. dce 2009 Review Instruction Formats ©2009, CE Department 16
  17. dce 2009 R-Format Instructions • Read two register operands • Perform arithmetic/logical operation • Write register result ©2009, CE Department
  18. dce 2009 Load/Store Instructions • Read register operands • Calculate address using 16-bit offset g – Use ALU, but sign-extend offset • Load: Read memory and update register • Store: Write register value to memory ©2009, CE Department
  19. dce 2009 Branch Instructions • Read register operands • Compare operands – Use ALU, subtract and check Zero output • Calculate target address – Sign-extend displacement – Shift left 2 places (word displacement) – Add to PC + 4 • Already calculated by instruction fetch ©2009, CE Department
  20. dce 2009 Branch Instructions Just re-routes re routes wires Sign bit Sign-bit wire replicated ©2009, CE Department
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