EMICONDUCTOR ( P N JUNCTION ) D IODES

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EMICONDUCTOR ( P N JUNCTION ) D IODES

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Physically, diodes are formed by the interface between two regions of oppositely doped semiconductor (i.e., pn junction) and are thus, structurally, the simplest semiconductor devices used in electronics. 1. Ideal Diode An ideal diode is a two-terminal device defined by the following non-linear (currentvoltage) iv-characteristic: i "electronic check valve" "arrowhead" i "brick wall" Anode + v - Cathode Reverse Bias "RB" Forward Bias "FB" Circuit Symbol 0 Forward Biased Regime (v0): Zero voltage drop occurs across a forward-biased ideal diode (i.e., the diode behaves like an ideal short circuit). Reverse Bias Regime (v≤0): Zero current flows in a reverse-biased ideal diode (i.e., the diode behaves like an open circuit)....

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  1. ELEC 254 S EMICONDUCTOR ( P N JUNCTION ) D IODES Physically, diodes are formed by the interface between two regions of oppositely doped semiconductor (i.e., pn junction) and are thus, structurally, the simplest semiconductor devices used in electronics. 1. Ideal Diode An ideal diode is a two-terminal device defined by the following non-linear (current- voltage) iv-characteristic: i "electronic check valve" "arrowhead" "brick wall" i Reverse Forward Anode Cathode Bias Bias + v - "RB" "FB" Circuit Symbol 0 v Forward Biased Regime (v>0): Zero voltage drop occurs across a forward-biased ideal diode (i.e., the diode behaves like an ideal short circuit). Reverse Bias Regime (v≤0): Zero current flows in a reverse-biased ideal diode (i.e., the diode behaves like an open circuit). Note: From the above, it follows that zero power dissipation occurs in an ideal diode. 2. Real Diode The physics of real pn junctions leads to the following (non-ideal) iv-characteristics: (see Figs. 3.7, 3.8 in S&S 4th ed. - Real Diode current-voltage characteristics) Forward Bias Regime (v>0): The iv-characteristic in this region is closely approximated by ( i = I s e v/ nVT − 1 ) where Is=Reverse Saturation Current (also called Scale Current in S&S text, since Is∝A). Typically, Is is very small: pA for small Si diodes, fA for IC diodes. 1
  2. Sedra & Smith, 4th Ed. Sedra & Smith, 4th Ed.
  3. 2  Dp Dn  2 I s = Aq  + ni =constant for a given diode at a given temperature.  L p N D Ln N A  n=empirical constant (typically 1≤n≤2, depending on the type of diode and its physical structure), which accounts for carrier gen/recomb in the depletion region (higher J's and fewer centers in IC's, so n is closer to 1, cf. 2 for discrete devices). Actually n depends on the magnitude of v & so is not strictly constant. VT=Volt-Equivalent of Temperature or Thermal Voltage. The Thermal Voltage can also be written explicitly as VT=kT/q where k=Boltzmann's constant (also written kB)=1.38x10-23 J/K T=Absolute Temperature (K) q=Electronic Charge=1.602x10-19 C. e.g. At 20 ˚C, VT=25.2 mV ≈25 mV (used throughout S&S text and this course). Clearly, for larger currents (where i>>I s or v>10nVT) i ≅ I sev / nVT which has been found to hold over several (≈7) decades of current. The diode equation has 2 parameters and hence 2 measurements are required to determine Is and n empirically. Consider the change in diode voltage drop due to a change in diode current: Let I1 = Is eV1/nVT and I 2 = Is eV2 /nVT , then I1/I 2 = e( V1− V )/nVT 2 or V1 − V2 = 2.303nVT log(I1/I 2 ) - so slope of log plot yields value of n i.e., the diode voltage changes by ≈2.3nVT for every decade change in diode current (e.g., ≈60 mV for n=1 @20 ˚C). In practice, if n is unknown, a common "rule of thumb" is to assume V1-V2≈100 mV/decade @ 20 ˚C, which yields n≈1.7 (in this course, if n is unknown, use n=1). Reverse Bias Regime (VZK≤ v≤0): The reverse diode current is also described by ( i = I s e v/ nVT − 1 )
  4. 3 but, since e v/nV T → 0 when v
  5. Sedra & Smith, 4th Ed.
  6. 4 Breakdown Regime: The temperature coefficient of Zener diodes depends on both voltage and current. Note: sometimes "TC" is called "Temco". TC mV/˚C Vz=6.8 V Vz=5.1 V 0 i Note: A 6.8 V Zener diode exhibits a TC≈+2 mV/˚C, which is complementary to a forward biased diode! 0.7 V 6.8 V + ≈7.5 V - ← nearly independent of T (over a useful range of i) 3. Diode Models & Analysis of Diode Circuits e.g. Consider the following circuit: I R + VDD VDD = IR + V (1) 10 kΩ V 10 V I = IS (e V/ nVT − 1) (2) - Exact Solution: If Is and n for the diode are known, then (1) and (2) can be solved simultaneously to obtain I and V. Graphical Solution: If data are available, then (1) and (2) could be plotted and I and V could be obtained from the intersection. i a similar graphical method is used Load Line for the analysis of transistors - later VDD /R Quiescent (Operating) Point, Q I 0 V VDD v
  7. 5 Approximate Solution: If an exact solution is not required, an approximation can be found using an iterative approach: e.g. Suppose the diode is specified as exhibiting a 0.7 V drop at 1 mA (in the text, this is sometimes called "a 1-mA diode" for short), with n=1.8. step 0) Assume that the diode can be adequately described by I ≅ Ise V/nVT (2') Substitute I=1 mA and V=0.7 V (from specs.) to calculate Is I s = 10 −3 e −0.7/nVT which yields I = 10 −3e (V−0.7)/nVT or V = nVT ln(I /10 −3 ) + 0.7 (2'') step 1) As a first guess/approximation, assume V=0.7 V, V − V 10 V - 0.7 V then I = DD = = 0.93 mA R 10 kW The accuracy can be improved by iterating between (1) and (2'') as follows: step 2) Substitute the value of I found in step 1 into (2'') to calculate a new value for V V = (1.8)(0.025)ln(0.93) + 0.7 = 696.7 mV step 3) Substitute this value back into (1), to calculate a new value for I 10 V - 0.697 V I= = 0.9303 mA 10 kW step 4) Continue iterating between (1) and (2'') until (I n − In−1 ) ≤ 1% (arbitrary precision) In Graphical representation of iterative method: i Load Line (1) V /R DD (2) .9303 3 4 5 .93 2 1 0 .697 .7 VDD v
  8. 6 Alternatively, appropriate simplifying assumptions can yield an approximate solution. Diode Models (for approximate analyses): 1. Exponential Model (I D = Ise VD /nVT ) 2. Ideal Diode Model  3. Constant-Voltage-Drop Model  Linearized Models 4. Piecewise-Linear (or Battery-plus-Resistance) Model  5. Small-Signal Model (later) (see Figs. 3.1, 3.24, 3.21 of S&S 4th ed. - linearized "Large-Signal" diode models) The choice of which model to apply in a given design/analysis depends on the operating point of the diode and the magnitude of the other voltages and currents in the circuit. e.g. Ideal Diode: may be adequate if VD is negligible compared to other voltages & currents in the circuit. Constant-Voltage-Drop: gives a reasonable approximation at higher currents Piecewise-Linear: is useful at smaller currents (gives significant error at higher currents) Small-Signal Model: Consider the following prototype circuit: + vd (t) i D (t) v D(t ) = VD + v d (t ) vD (t) VD i D(t ) = IS ev D (t )/ nVT - The expression for i D(t) can be expanded in a Taylor series about the operating point to obtain  v (t)  iD(t) ≈ ID 1 + d  Small-Signal Approximation  nVT  f(x o ) (x − xo ) (x − xo )2 (Recall: f (x) = + f '( xo ) + f ′′(xo ) + L) 0! 1! 2! where I D = Ise VD /nVT = diode current when v d(t)≡0, which remains a good approximation provided
  9. 7 vd
  10. 8 Simple Half-Wave Rectifiers: VDO could be any dc bias voltage! rD + Ideal + VDO vi R vo - Real Diode -  R  vi = Vi sin(ωt) vo =   (v i − VD0 ) ; vi ≥ VD0  R + rD  = 0 ; v i < VD0 Peak Inverse Voltage, PIV = Maximum reverse bias voltage that D must withstand without breakdown (e.g., v i for the circuit above). Conduction Angle, 2θ = 2cos −1 ( VD0 / V) (describes what fraction of ωΤ diode is "on"). vo If D is Ideal V 0 ωt vi = Vsinωt vo If D is Real V RL (V − V ) VDO DO R L + rD 0 ωt Threshold for conduction occurs at -V Vcosθ = VDO or Vsin (π 2 -θ ) = VDO 2θ Conduction Angle ∴ 2θ = 2 cos-1 VDO V Aside: Effect of non-ideal characteristic is to cause distortion in the output waveform In practise, v i is usually taken from the secondary winding of an appropriate transformer in order to efficiently set the desired amplitude and ensure isolation from the power distribution system.
  11. 9 Simple Full-Wave Rectifiers: (see Figs. 3.38, 3.39 of S&S 4th ed. - FW Rectifiers ) Rectifier Circuits with Peak Detection: Consider the following HW rectifier circuit with the load resistance replaced by a capacitor: vi Vp 0 ωt D + + vi C vo vo - - Vp 0 ωt This circuit can be viewed as a peak detector with an infinite load resistance. If the diode is considered to be ideal, then v o is clamped at Vp. In practical circuits, some finite load resistance always exists (e.g., input impedance of subsequent stages), through which C can discharge during the diode "off cycle". D + + vi C RL vo - - v i(t)=Vp cos(ωt) assuming the capacitor and resistor are ideal, and that a steady-state is reached prior to t=0 vo Vr τ= RLC Vp 0 ωt vi If RLC>>2π/ω, then Vr
  12. 10 Peak Rectifiers: (see separate set of notes focusing on analysis of HW Peak Rectifier) 5. Other Diode-Capacitor Circuits Clamped Capacitor (dc Restorer) C + + vi vc D RL v o - - 1) If RL→∞ and the diode & capacitor are ideal: D is forward biased only when v i
  13. 11 vo +Vp -Vp' +Vp -Vp' 0 t Voltage Doubler: Consider a clamped capacitor "module" cascaded with a peak-detector "module" as shown: C1 D2 + + vi vc D1 C2 vo - - The clamping circuit determines VD1, which becomes the input to the peak rectifier/detector.
  14. 12 vi = Vs sin t ω vi Vs 0 ωt vD1 2 Vs Vs 0 ωt vo 2 Vs Vs 0 ωt If C1 and D1 are ideal, then C1 will charge to -Vs, which provides a dc offset of Vs to the signal passed to the peak rectifier and C2 will charge to 2Vs (i.e., the "peak" voltage passed from the clamp). If C2 and D2 are ideal, then Vo= 2Vs=constant. Alternatively, C1 D2 + + vi vc D1 C2 vo - - If C1 and D1 are ideal, then C1 will charge to Vs, which provides a dc offset of -Vs to the signal passed to the peak rectifier and C2 will charge to -2Vs (i.e., the negative "peak" voltage passed from the clamp). If C2 and D2 are ideal, then Vo=-2Vs=constant. Limiting or Clipping Circuits: The general transfer characteristic of a limiter circuit is described by...
  15. 13 v o = Kv i ; L-/K ≤ v i ≤ L+ /K (i.e., linear) = L+ ; v i > L+ /K = L- ; v i < L-/K or, graphically vo "hard" limiting L+ "soft" limiting K 1 L-/K L+/K vi L- Passive Limiter: 0 < |K| < 1 Active Limiter: 0 < |K| (more about this later!) Limiting circuits can be realized using regular or Zener diodes and resistors in various configurations. (see Fig. 3.46 of S&S 4th ed. - various basic limiter circuits)
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