Logic Design with VHDL

Chia sẻ: Nguyen Huu Hai | Ngày: | Loại File: PDF | Số trang:438

1
778
lượt xem
354
download

Logic Design with VHDL

Mô tả tài liệu
  Download Vui lòng tải xuống để xem tài liệu đầy đủ

Logic Design with VHDL

Chủ đề:
Lưu

Nội dung Text: Logic Design with VHDL

  1. Figure 1-1 Basic Gates A A C C B B AND: C = A B OR: C = A + B A A C C B NOT: C = A' EXCLUSIVE OR: C = A + B
  2. Figure 1-2 Full Adder X Y Cin Cout Sum 0 00 0 0 0 01 0 1 Cout X 0 10 0 1 FULL 0 11 1 0 Y ADDER 1 00 0 1 Cin Sum 1 01 1 0 1 10 1 0 1 11 1 1 (a) Full adder module (b) Truth Table Sum = X'Y'Cin + X'YCin' + XY'Cin' + XYCin = X + Y + Cin Cout = X'YCin + XY'Cin + XYCin' + XYCin = XY + XCin + YCin
  3. Figure 1-3 Four-Variable Karnaugh Maps AB AB four corner terms CD 00 01 11 10 CD 00 01 11 10 combine to give B' D' 00 00 1 0 0 1 0 4 12 8 01 C 01 1 0 1 5 13 9 0 0 A'BD 11 11 1 X 1 3 1 7 15 11 10 10 2 1 1 X 1 6 14 10 F =∑m(0,2,3,5,6,7,8,10,11) + ∑d(14,15) = C + B' D' + A' BD = (B' + C + D) (B + C + D') (A'+B')
  4. Figure 1-4 Selection of Prime Implicants AB 00 01 11 10 CD 00 1 X 0 8 4 12 A'C' 01 1 1 1 9 5 13 11 1 1 1 ACD 3 15 11 7 10 X 1 2 6 14 10 A'B'D' F = A'C' + A'B'D' + ACD + A'BD or F = A'C' + A'B'D' + ACD + BCD
  5. Figure 1-5 Simplification Using Map-Entered Variables AB AB AB AB CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10 00 1 00 00 X 00 X 1 01 01 01 01 X E X F X X X 1 X X X 1 11 11 11 11 1 1 1 X X X X E 1 1 X X 1 1 10 10 10 10 1 X 1 X X X X X G E=F=0 E = 1, F = 0 E = 0, F = 1 MS 0 = A'B' + ACD MS 1 = A'D MS 2 = AD G = MS0 + EMS 1 + FMS 2 = A'B' + ACD + EA'D + FAD
  6. Figure 1-6 NAND and NOR Gates NAND: A A C C C = (AB)' = A' + B' B B NOR: A A C C C = (A+B)' = A'B' B B
  7. Figure 1-7 Conversion to NOR Gates A G B' C Z D E F (a) AND-OR network Double inversion cancels A B' C' D G' Z Complemented input E cancels inversion F (b) Equivalent NOR-gate network
  8. Figure 1-8 Conversion of AND-OR Network to NAND Gates A B C D F E (a) AND_OR network Bubbles cancel A B C D F E (b) First step in NAND conversion Added inverter Added inverter A B' C D' F E' (c) Completed conversion
  9. Figure 1-9 Elimination of 1-Hazard A D A BC B F 0 1 00 0 1 E C F = AB' + BC 01 0 1 1 - Hazard (a) Network with 1-hazard 11 1 1 10 0 0 B' B D E F 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns (b) Timing Chart A A BC B 0 1 00 0 1 F C 01 0 1 11 1 1 A F = AB' + BC + AC 10 0 0 (c) Network with hazard removed
  10. Figure 1-10 Clocked D Flip-flop with Rising-edge Trigger Q' Q Q+ DQ 0 0 0 DFF 0 1 0 1 0 1 1 1 1 CLK D Q+ = D
  11. Figure 1-11 Clocked J-K Flip-flop Q+ J K Q 0 0 0 0 0 0 1 1 Q' Q 0 1 0 0 FF 0 1 1 0 CK 1 0 0 1 K J 1 0 1 1 1 1 0 1 1 1 1 0 Q + = JQ' + K'Q
  12. Figure 1-12 Clocked T Flip-flop Q' Q Q+ TQ 0 0 0 FF 0 1 1 1 0 1 1 1 0 CLK T Q+ = QT' + Q'T = Q + T
  13. Figure 1-13 S-R Latch Q+ S R Q S P 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 Q 1 1 0 – R 1 1 1 – Q += S + R'Q
  14. Figure 1-14 Transparent D Latch Q+ G D Q 0 0 0 0 0 0 1 1 Q 0 1 0 0 Latch 0 1 1 1 1 0 0 0 G D 1 0 1 0 1 1 0 1 1 1 1 1
  15. Figure 1-15 Implementation of D Latch D G Q+ = DG + G'Q + (DQ) Q D
  16. Figure 1-16 General Model of Mealy Sequential Machine Outputs (Z) Inputs (X) Combinational Next state Network State State Reg clock
  17. Figure 1-17 State Graph and Table for Code Converter t0 S0 NS Z 0/1 1/0 t1 S2 C X=0 X=1 PS X=0 X=1 NC S1 1/0 S0 S1 S2 1 0 0/1 0/0,1/1 0/1 0/0,1/1 S1 S3 S4 1 0 S2 S4 S4 0 1 t2 S4 C S3 NC S3 S5 S5 0 1 S4 S5 S6 1 0 0/1 1/0 0/0,1/1 S5 S0 S0 0 1 S6 S0 – 1 – t3 S5 S6 C NC (b) State Table (a) Mealy state graph
  18. From Page 20 I. States which have the same next state (NS) for a given input should be given adjacent assignments (look at the columns of the state table). II. States which are the next states of the same state should be given adjacent assignments (look at the rows). III. States which have the same output for a given input should be given adjacent assignments. I. (1,2) (3,4) (5,6) (in the X=1 column, S1 and S2 both have NS S4; in the X=0 column, S3 & S4 have NS S5, and S5 & S6 have NS S0) II. (1,2) (3,4) (5,6) (S1 & S2 are NS of S0; S3 & S4 are NS of S1; and S5 & S6 are NS of S4) III. (0,1,4,6) (2,3,5) Q1 0 1 Q2 Q3 00 S0 S1 Figure 1-18(a) 01 S2 State Assignment Map 11 S5 S3 10 S6 S4
  19. Figure 1-17(b) State Table Figure 1-18(b) Transition Table NS Z Q1:Q2:Q3: Z PS X=0 X=1 X=0 X=1 Q1Q2Q3 X=0 X=1 X=0 X=1 S0 S1 S2 1 0 000 100 101 1 0 S1 S3 S4 1 0 100 111 110 1 0 S2 S4 S4 0 1 101 110 110 0 1 S3 S5 S5 0 1 111 011 011 0 1 S4 S5 S6 1 0 110 011 010 1 0 S5 S0 S0 0 1 011 000 000 0 1 S6 S0 – 1 – 010 000 xxx 1 x 001 xxx xxx x x S0 = 000, S1 = 100, S2 = 101, S3 = 111, S4 = 110, S5 = 011, S6 = 010
  20. Figure 1-19 Karnaugh Maps for Figure 1-17 XQ 1 XQ1 Q 2Q 3 00 01 11 10 Q 2 Q 3 00 01 11 10 00 1 1 1 00 0 1 1 1 0 01 01 X 1 1 X X 1 1 X 11 11 0 0 0 0 0 0 1 1 10 10 0 0 0 X 0 1 1 X D 1 = Q1+ = Q2' D 2 = Q2+= Q1 XQ1 XQ1 Q 2Q 3 00 01 11 10 Q 2Q 3 00 01 11 10 00 0 1 0 1 00 1 1 0 0 01 01 X 0 0 X X 0 1 X 11 11 0 1 1 0 0 0 1 1 10 10 0 1 0 X 0 X 1 1 D 3 = Q3+ = Q1Q 2Q 3 + X'Q1Q 3' + XQ1'Q 2' Z = X'Q3' + XQ3
Đồng bộ tài khoản