Microcontroller 8051

Chia sẻ: anhkong

The microprocessor is the core of computer systems. Nowadays many communication, digital entertainment, portable devices, are controlled by them. A designer should know what types of components he needs, ways to reduce production costs and product reliable. CPU is stand-alone, RAM, ROM, I/O, timer are separate.

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Nội dung Text: Microcontroller 8051

1
Why do we need to learn Microprocessors/controllers?


• The microprocessor is the core of computer
systems.
• Nowadays many communication, digital
entertainment, portable devices, are controlled by
them.
• A designer should know what types of
components he needs, ways to reduce production
costs and product reliable.


2
Different aspects of a microprocessor/controller



• Hardware :Interface to the real world




• Software :order how to deal with inputs




3
The necessary tools for a microprocessor/controller

• CPU: Central Processing Unit
• I/O: Input /Output
• Bus: Address bus & Data bus
• Memory: RAM & ROM
• Timer
• Interrupt
• Serial Port
• Parallel Port


4
Microprocessors:
General-purpose microprocessor
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example Intel’s x86, Motorola’s 680x0



Many chips on mother’s board
Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

5
Microcontroller :
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X




CPU RAM ROM
A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller

6
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, RAM,
• CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate
timer are all on a single chip
• designer can decide on the
amount of ROM, RAM and I/O • fix amount of on-chip ROM,
ports. RAM, I/O ports
• expansive • for applications in which cost,
• versatility power and space are critical
• general-purpose • single-purpose




7
Embedded System

• Embedded system means the processor is embedded into that application.
• An embedded product uses a microprocessor or microcontroller to do one
task only.
• In an embedded system, there is only one application software that is
typically burned into ROM.
• Example E printer, keyboard, video game player




8
Three criteria in Choosing a Microcontroller

1. meeting the computing needs of the task efficiently and cost effectively
• speed, the amount of ROM and RAM, the number of I/O ports and
timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
2. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator, technical
support
3. wide availability and reliable sources of the microcontrollers.




9
Block Diagram

External interrupts
On-chip Timer/Counter

Interrupt ROM for
On-chip Timer 1 Counter
Control program
code RAM Timer 0 Inputs


CPU


Bus Serial
4 I/O Ports
OSC Control Port


P0 P1 P2 P3 TxD RxD
Address/Data

10
11
Pin Description of the 8051

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0
P1.2 3 38 P0.1(AD1)
)
P1.3 4 8051 37 P0.2(AD2
P0.3(AD3)
P1.4 5 36 )
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8) 

12
Packing Types of 8051

• The 8051 family members come in different
packages, such as DIP dual in-line
package p ,QFP , quad flat package q and
LLC L leadless chip carrier l .
– See Appendix H Pages 427-429 P
• They all have 40 pins.
• Figure 4-1. 8051 Pin Diagram



13
8051 Pin Diagram
PDIP/Cerdip

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0
P1.2 3 38 ) 0.1(AD1)
P
P1.3 4 8051 37 P0.2(AD2
) 0.3(AD3)
P1.4 5 36 P
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8) 14
Pins of 8051 1/4 1

• Vcc V pin 40 p i
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND G pin 20 p i ground
• XTAL1 and XTAL2 X pins 19,18 p i
– These 2 pins provide external clock.
– Way 1 W using a quartz crystal oscillator 
– Way 2 W using a TTL oscillator 
– Example 4-1 shows the relationship between XTAL and the
machine cycle. 
15
Pins of 8051 P 2/4 2

• RST R pin 9 p i reset
– It is an input pin and is active high I normally low n .
• The high pulse must be high at least 2 machine cycles.
– It is a power-on reset.
• Upon applying a high pulse to RST, the microcontroller will reset
and all values in registers will be lost.
• Reset values of some 8051 registers 
– Way 1 W Power-on reset circuit 
– Way 2 W Power-on reset with debounce 



16
Pins of 8051 P 3/4 3

• /EA / pin 31 p i external access
– There is no on-chip ROM in 8031 and 8032 .
– The /EA pin is connected to GND to indicate the code is
stored externally.
– /PSEN  ALE are used for external ROM.
– For 8051, /EA pin is connected to Vcc.
– “/” means active low.
• /PSEN / pin 29 p i program store enable
– This is an output pin and is connected to the OE pin of the
ROM.
– See Chapter 14. 17
Pins of 8051 P 4/4 4

• ALE A pin 30 p i address latch enable
– It is an output pin and is active high.
– 8051 port 0 provides both address and data.
– The ALE pin is used for de-multiplexing the address and
data by connecting to the G pin of the 74LS373 latch.
• I/O port pins
– The four ports P0, P1, P2, and P3.
– Each port uses 8 pins.
– All I/O pins are bi-directional.


18
Figure 4-2 (a). XTAL Connection to 8051

• Using a quartz crystal oscillator
• We can observe the frequency on the XTAL2 pin.
C2
XTAL2
30pF

C1
XTAL1
30pF

GND
 19
Figure 4-2 (b). XTAL Connection to an
External Clock Source
• Using a TTL oscillator
• XTAL2 is unconnected.

NC XTAL2


EXTERNAL
OSCILLATOR XTAL1
SIGNAL


GND

 20
Example 4-1
Find the machine cycle for
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.

Solution:

(a) 11.0592 MHz / 12 = 921.6 kHz;
machine cycle = 1 / 921.6 kHz = 1.085 µs
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 µs



 21
Table 4-1: RESET Value of Some 8051
Registers

Register Reset Value
PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000

RAM are all zero.
 22
Figure 4-3 (a). Power-On RESET Circuit
Vcc


+

10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST




 23
Figure 4-3 (b). Power-On RESET with
Debounce
Vcc



31
EA/VPP
X1
10 uF 30 pF

X2
RST
9
8.2 K



 24
Pins of I/O Port

• The 8051 has four I/O ports
– Port 0 P pins 32-39 p i P0 P P0.0 P P0.7 P
– Port 1 P pins 1-8 p i P1 P P1.0 P P1.7 P
– Port 2 P pins 21-28 p i P2 P P2.0 P P2.7 P
– Port 3 P pins 10-17 p i P3 P P3.0 P P3.7 P
– Each port has 8 pins.
• Named P0.X N X=0,1,...,7 X , P1.X, P2.X, P3.X
• Ex E P0.0 is the bit 0 P LSB L of P0
• Ex E P0.7 is the bit 7 P MSB M of P0
• These 8 bits form a byte.
• Each port can be used as input or output (bi-
25
direction).
Port 1 P pins 1-8 p

• Port 1 is denoted by P1.
– P1.0 ~ P1.7
• We use P1 as examples to show the operations on
ports.
– P1 as an output port (i.e., write CPU data to the external pin)
– P1 as an input port (i.e., read pin data into CPU bus)




26
A Pin of Port 1


Read latch Vcc
TB2

Load(L1)
Internal CPU D Q P1.X
bus P1.X pin

Write to latch Clk Q M1




TB1
Read pin P0.x
8051 IC 27
Hardware Structure of I/O Pin

• Each pin of I/O ports
– Internal CPU bus I communicate with CPU
– A D latch store the value of this pin
• D latch is controlled by “Write to latch”
– Write to latch W 1 1 write data into the D latch
– 2 Tri-state buffer 2 2
• TB1: controlled by “Read pin”
– Read pin R 1 1 really read the data present at the pin
• TB2: controlled by “Read latch”
– Read latch R 1 1 read value from internal latch
– A transistor M1 gate
• Gate=0: open
28
• Gate=1: close
Figure C-9. Tri-state Buffer


Output Input



Tri-state control
(active high)



L L H H Low



H H Highimpedance
(open-circuit)


 29
Writing “1” to Output Pin P1.X


Read latch Vcc
TB2
2. output pin
1. write a 1 to the pin Load(L1) is Vcc
D Q 1 P1.X
Internal CPU
bus P1.X pin
0 output 1
Write to latch Clk Q M1




TB1
Read pin


8051 IC 30
Writing “0” to Output Pin P1.X


Read latch Vcc
TB2
2. output pin
1. write a 0 to the pin Load(L1) is ground
D Q 0 P1.X
Internal CPU
bus P1.X pin
1 output 0
Write to latch Clk Q M1




TB1
Read pin


8051 IC 31
Port 1 as Output P Write to a Port W

• Send data to Port 1 S
MOV A,#55H
BACK: MOV P1,A
ACALL DELAY
CPL A
SJMP BACK
– Let P1 toggle.
– You can write to P1 directly.


32
Reading Input v.s. Port Latch

• When reading ports, there are two possibilities W
– Read the status of the input pin. R from external pin
value v
• MOV A, PX
• JNB P2.1, TARGET ; jump if P2.1 is not set
• JB P2.1, TARGET ; jump if P2.1 is set
• Figures C-11, C-12
– Read the internal latch of the output port.
• ANL P1, A ; P1 ← P1 AND A
• ORL P1, A ; P1 ← P1 OR A
• INC P1 ; increase P1
• Figure C-17
33
• Table C-6 Read-Modify-Write Instruction (or Table 8-5)
Figure C-11. Reading “High” at Input Pin


Read latch Vcc 2. MOV A,P1
TB2
1. write a 1 to the pin external
MOV P1,#0FFH Load(L1) pin=High
D Q 1 1 P1.X
Internal CPU
bus P1.X pin

Clk Q 0 M1
Write to latch




TB1
Read pin
3. Read pin=1
Read latch=0 8051 IC 34
Write to latch=1
Figure C-12. Reading “Low” at Input Pin


Read latch Vcc 2. MOV A,P1
TB2
1. write a 1 to the pin
external
Load(L1)
MOV P1,#0FFH pin=Low
D Q 1 0 P1.X
Internal CPU
bus P1.X pin

Clk Q 0 M1
Write to latch




TB1
Read pin
3. Read pin=1
Read latch=0 8051 IC 35
Write to latch=1
Port 1 as Input P Read from Port R

• In order to make P1 an input, the port must be
programmed by writing 1 to all the bit.
MOV A,#0FFH ;A=11111111B
MOV P1,A ;make P1 an input
port
BACK: MOV A,P1 ;get data from P0
MOV P2,A ;send data to P2
SJMP BACK
– To be an input port, P0, P1, P2 and P3 have similar methods.

36
Table 8-4: Instructions For Reading an Input
Port
• Following are instructions for reading external pins of
ports:

Mnemonics Examples Description
MOV A,PX MOV A,P2 Bring into A the data at
P2 pins
JNB JNB P2.1,TARGET Jump if pin P2.1 is low
PX.Y,..
JB PX.Y,.. JB P1.3,TARGET Jump if pin P1.3 is high

MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to
CY 37
Figure C-17. Reading the Latch
1. Read pin=0 Read latch=1
Write to latch=0 (Assume
P1.X=0 initially)
Read latch Vcc
TB2
2. CPU compute 4. P1.X=1
0 Load(L1)
P1.X OR 1
D Q 0 1 P1.X
Internal CPU
bus P1.X pin
1 0
Write to latch Clk Q M1
3. write result to latch
Read pin=0
Read latch=0
Write to latch=1 TB1
Read pin


8051 IC 38
Reading Latch

• Exclusive-or the Port 1 E
MOV P1,#55H ;P1=01010101
ORL P1,#0F0H ;P1=11110101
1. The read latch activates TB2 and bring the data
from the Q latch into CPU.
• Read P1.0=0
2. CPU performs an operation.
• This data is ORed with bit 1 of register A. Get 1.
3. The latch is modified.
• D latch of P1.0 has value 1.
4. The result is written to the external pin. 39
Read-modify-write Feature

• Read-modify-write Instructions
– Table C-6
• This features combines 3 actions in a single
instruction i
1. CPU reads the latch of the port
2. CPU perform the operation
3. Modifying the latch
4. Writing to the pin
– Note that 8 pins of P1 work independently.

40
Port 1 as Input P Read from latch R

• Exclusive-or the Port 1 E
MOV P1,#55H ;P1=01010101
AGAIN: XOR P1,#0FFH ;complement

ACALL DELAY
SJMP AGAIN
– Note that the XOR of 55H and FFH gives AAH.
– XOR of AAH and FFH gives 55H.
– The instruction read the data in the latch (not from the pin).
– The instruction result will put into the latch and the pin.
41
– P1 is configured as an output port.
Table C-6 T Read-Modify-Write Instructions
Mnemonics Example
ANL ANL P1,A
ORL ORL P1,A
XRL XRL P1,A
JBC PX.Y, TARGET JBC P1.1, TARGET
CPL CPL P1.2
INC INC P1
DEC DEC P1
DJNZ PX, TARGET DJNZ P1,TARGET
MOV PX.Y,C MOV P1.2,C
CLR PX.Y CLR P1.3
SETB PX.Y SETB P1.4 42
Questions

• How to write the data to a pin H
• How to read the data from the pin H
– Read the value present at the external pin.
• Why we need to set the pin first W
– Read the value come from the latch R not from the external
pin p .
• Why the instruction is called read-modify write?




43
Other Pins

• P1, P2, and P3 have internal pull-up resisters.
– P1, P2, and P3 are not open drain.
• P0 has no internal pull-up resistors and does not
connects to Vcc inside the 8051.
– P0 is open drain.
– Compare the figures of P1.X and P0.X. 
• However, for a programmer, it is the same to program
P0, P1, P2 and P3.
• All the ports upon RESET are configured as output.

44
A Pin of Port 0


Read latch
TB2



Internal CPU D Q P0.X
bus P1.X pin

Write to latch Clk Q M1




TB1
Read pin 
P1.x
8051 IC 45
Port 0 P pins 32-39 p

• P0 is an open drain.
– Open drain is a term used for MOS chips in the same way
that open collector is used for TTL chips.
• When P0 is used for simple data I/O we must connect
it to external pull-up resistors.
– Each pin of P0 must be connected externally to a 10K ohm
pull-up resistor.
– With external pull-up resistors connected upon reset, port 0
is configured as an output port.


46
Figure 4-4. Port 0 with Pull-Up Resistors



Vcc
10 K

P0.0
DS5000 P0.1




Port 0
P0.2
8751 P0.3
8951 P0.4
P0.5
P0.6
P0.7

47
Dual Role of Port 0

• When connecting an 8051/8031 to an external
memory, the 8051 uses ports to send addresses and
read instructions.
– 8031 is capable of accessing 64K bytes of external memory.
– 16-bit address 1 P0 provides both address A0-A7, P2
provides address A8-A15.
– Also, P0 provides data lines D0-D7.
• When P0 is used for address/data multiplexing, it is
connected to the 74LS373 to latch the address.
– There is no need for external pull-up resistors as shown in
Chapter 14.
48
Figure 14-9 74LS373

PSEN OE
ALE 74LS373 OC
G
P0.0 A0
D
P0.7 A7


D0
D7
EA


P2.0 A8
P2.7 A15

8051 ROM 49
Reading ROM (1/2)
2. 74373 latches
1. Send address
the address and
to ROM
PSEN send to ROM OE
ALE 74LS373 OC
G
P0.0 A0
D
P0.7 Address A7


D0
D7
EA


P2.0 A8
P2.7 A12

8051 ROM 50
Reading ROM (2/2)
2. 74373 latches
the address and
PSEN send to ROM OE
ALE 74LS373 OC
G
P0.0 A0
D
P0.7 Address A7


D0
D7
EA 3. ROM send the
instruction back
P2.0 A8
P2.7 A12

8051 ROM 51
ALE Pin

• The ALE pin is used for de-multiplexing the address
and data by connecting to the G pin of the 74LS373
latch.
– When ALE=0, P0 provides data D0-D7.
– When ALE=1, P0 provides address A0-A7.
– The reason is to allow P0 to multiplex address and data.




52
Port 2 P pins 21-28 p

• Port 2 does not need any pull-up resistors since it
already has pull-up resistors internally.
• In an 8031-based system, P2 are used to provide
address A8-A15.




53
Port 3 P pins 10-17 p

• Port 3 does not need any pull-up resistors since it
already has pull-up resistors internally.
• Although port 3 is configured as an output port upon
reset, this is not the way it is most commonly used.
• Port 3 has the additional function of providing
signals.
– Serial communications signal S RxD, TxD R Chapter
10 1
– External interrupt E /INT0, /INT1 / Chapter 11 C
– Timer/counter T T0, T1 T Chapter 9 C
– External memory accesses in 8031-based system E /WR, 54
/RD / Chapter 14 C
Table 4-2: Port 3 Alternate Functions
P3 Bit Function Pin


P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17
55
I/O Programming; Bit Manipulation




56
I/O Programming

• To toggle every bit of P1 continuously.
• 3 ways 3 Way 1, Way 2, and Way 3.
– Which one is better W




57
Way 1

• Send data to Port 1 through ACC S
BACK: MOV A,#55H ;A=01010101B
MOV P1,A
ACALL DELAY
MOV A,#0AAH ;A=10101010B
MOV P1,A
ACALL DELAY
SJMP BACK

58
Way 2

• Access Port 1 directly A
BACK: MOV P1,#55H ;P1=01010101B
ACALL DELAY
MOV P1,#0AAH ;P1=10101010B

ACALL DELAY
SJMP BACK



59
Way 3

• Read-modify-write feature R
MOV P1,#55H ;P1=01010101B
AGAIN: XRL P1,#0FFH
ACALL DELAY
SJMP AGAIN
– The instruction XRL P1,#0FFH do EX-OR P1 and FFH
That is, to toggle P1. T




60
Bit Manipulation

• Sometimes we need to access only 1 or 2 bits of the
port instead of the entire 8 bits.
• Table 4-3 shows how to name each pin for each I/O
port. 
• Example 4-2 
• See Section 8.1 single-bit instruction programming




61
Table 4-3: Single-Bit Addressability of Ports

P0 P1 P2 P3 Port Bit
P0.0 P1.0 P2.0 P3.0 D0
P0.1 P1.1 P2.1 P3.1 D1
P0.2 P1.2 P2.2 P3.2 D2
P0.3 P1.3 P2.3 P3.3 D3
P0.4 P1.4 P2.4 P3.4 D4
P0.5 P1.5 P2.5 P3.5 D5
P0.6 P1.6 P2.6 P3.6 D6
P0.7 P1.7 P2.7 P3.7 D7
 62
Example 4-2
Write a program to perform the following.
(a) Keep monitoring the P1.2 bit until it becomes high,
(b) When P1.2 becomes high, write value 45H to port 0, and
(c) Send a high-to-low (H-to-L) pulse to P2.3.
Solution:
SETB P1.2 ;make P1.2 an input
MOV A,#45H ;A=45H
AGAIN:JNB P1.2,AGAIN;get out when P.2=1
MOV P0,A ;issue A to P0
SETB P2.3 ;make P2.3 high
CLR P2.3 ;make P2.3 low for H-to-L
Note N
1. JNB: jump if no bit 1 jump if P1.2 = 0 j  
2. a H-to-L pulse by the sequence of instructions SETB and CLR.
63
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