In this section, we discuss how to build practical digital circuits, using switch-level
11.2.1 CMOS Nor Gate
Though Verilog has a nor gate primitive, let us design our own nor gate,using
CMOS switches. The gate and the switch-level circuit diagram for the nor gate are
shown in Figure 11-4.
Figure 11-4. Gate and Switch Diagram for Nor Gate
Using the switch primitives discussed in Section 11.1, Switch-Modeling Elements,
the Verilog description of the circuit is shown in Example 11-4 below.
Example 11-4 Switch-Level Verilog for Nor Gate
//Define our own nor gate, my_nor
module my_nor(out, a, b);
input a, b;
//set up power and ground lines
supply1 pwr; //pwr is connected to Vdd (power supply)
supply0 gnd ; //gnd is connected to Vss(ground)
//instantiate pmos switches
pmos (c, pwr, b);
pmos (out, c, a);
//instantiate nmos switches
nmos (out, gnd, a);
nmos (out, gnd, b);
We can now test our nor gate, using the stimulus shown below.
//stimulus to test the gate
reg A, B;
//instantiate the my_nor module
my_nor n1(OUT, A, B);
//test all possible combinations
A = 1'b0; B = 1'b0;
#5 A = 1'b0; B = 1'b1;
#5 A = 1'b1; B = 1'b0;
#5 A = 1'b1; B = 1'b1;
$monitor($time, " OUT = %b, A = %b, B = %b", OUT, A, B);
The output of the simulation is shown below.
0 OUT = 1, A = 0, B = 0
5 OUT = 0, A = 0, B = 1
10 OUT = 0, A = 1, B = 0
15 OUT = 0, A = 1, B = 1
Thus we designed our own nor gate. If designers need to customize certain library
blocks, they use switch-level modeling.
11.2.2 2-to-1 Multiplexer
A 2-to-1 multiplexer can be defined with CMOS switches. We will use the my_nor
gate declared in Section 11.2.1, CMOS Nor Gate to implement the not function.
The circuit diagram for the multiplexer is shown in Figure 11-5 below.
Figure 11-5. 2-to-1 Multiplexer, Using Switches
The 2-to-1 multiplexer passes the input I0 to output OUT if S = 0 and passes I1 to
OUT if S = 1. The switch-level description for the 2-to-1 multiplexer is shown in
Example 11-5 Switch-Level Verilog Description of 2-to-1 Multiplexer
//Define a 2-to-1 multiplexer using switches
module my_mux (out, s, i0, i1);
input s, i0, i1;
wire sbar; //complement of s
//create the complement of s; use my_nor defined previously.
my_nor nt(sbar, s, s); //equivalent to a not gate
//instantiate cmos switches
cmos (out, i0, sbar, s);
cmos (out, i1, s, sbar);
The 2-to-1 multiplexer can be tested with a small stimulus. The stimulus is left as
an exercise to the reader.
11.2.3 Simple CMOS Latch
We designed combinatorial elements in the previous examples. Let us now define a
memory element which can store a value. The diagram for a level-sensitive CMOS
latch is shown in Figure 11-6.
Figure 11-6. CMOS flipflop
The switches C1 and C2 are CMOS switches, discussed in Section 11.1.2, CMOS
Switches. Switch C1 is closed if clk = 1, and switch C2 is closed if clk = 0.
Complement of the clk is fed to the ncontrol input of C2. The CMOS inverters can
be defined by using MOS switches, as shown in Figure 11-7.
Figure 11-7. CMOS Inverter
We are now ready to write the Verilog description for the CMOS latch. First, we
need to design our own inverter my_not by using switches. We can write the
Verilog module description for the CMOS inverter from the switch-level circuit
diagram in Figure 11-7. The Verilog description of the inverter is shown below.
Example 11-6 CMOS Inverter
//Define an inverter using MOS switches
module my_not(out, in);
//declare power and ground
//instantiate nmos and pmos switches
pmos (out, pwr, in);
nmos (out, gnd, in);
Now, the CMOS latch can be defined using the CMOS switches and my_not
inverters. The Verilog description for the CMOS latch is shown in Example 11-6.
Example 11-7 CMOS Flipflop
//Define a CMOS latch
module cff ( q, qbar, d, clk);
output q, qbar;
input d, clk;
wire nclk; //complement of clock
//instantiate the inverter
my_not nt(nclk, clk);
//instantiate CMOS switches
cmos (e, d, clk, nclk); //switch C1 closed i.e. e = d, when clk = 1.
cmos (e, q, nclk, clk); //switch C2 closed i.e. e = q, when clk = 0.
//instantiate the inverters
my_not nt1(qbar, e);
my_not nt2(q, qbar);
We will leave it as an exercise to the reader to write a small stimulus module and
simulate the design to verify the load and store properties of the latch.