Sequential Verulog Topicspart 6

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Sequential Verulog Topicspart 6

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Sequential UDPs Sequential UDPs differ from combinational UDPs in their definition and behavior. Sequential UDPs have the following differences

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Nội dung Text: Sequential Verulog Topicspart 6

  1. 12.3 Sequential UDPs Sequential UDPs differ from combinational UDPs in their definition and behavior. Sequential UDPs have the following differences: • The output of a sequential UDP is always declared as a reg. • An initial statement can be used to initialize output of sequential UDPs. • The format of a state table entry is slightly different. • ..... : : ; • There are three sections in a state table entry: inputs, current state, and next state. The three sections are separated by a colon (:) symbol. • The input specification of state table entries can be in terms of input levels or edge transitions. • The current state is the current value of the output register. • The next state is computed based on inputs and the current state. The next state becomes the new value of the output register. • All possible combinations of inputs must be specified to avoid unknown output values. If a sequential UDP is sensitive to input levels, it is called a level-sensitive sequential UDP. If a sequential UDP is sensitive to edge transitions on inputs, it is called an edge-sensitive sequential UDP. 12.3.1 Level-Sensitive Sequential UDPs Level-sensitive UDPs change state based on input levels. Latches are the most common example of level-sensitive UDPs. A simple latch with clear is shown in Figure 12-3. Figure 12-3. Level-Sensitive Latch with clear In the level-sensitive latch shown above, if the clear input is 1, the output q is always 0. If clear is 0, q = d when clock = 1. If clock = 0, q retains its value. The latch can be described as a UDP as shown in Example 12-7. Note that the dash "-" symbol is used to denote no change in the state of the latch. Example 12-7 Verilog Description of Level-Sensitive UDP
  2. //Define level-sensitive latch by using UDP. primitive latch(q, d, clock, clear); //declarations output q; reg q; //q declared as reg to create internal storage input d, clock, clear; //sequential UDP initialization //only one initial statement allowed initial q = 0; //initialize output to value 0 //state table table //d clock clear : q : q+ ; ? ? 1 : ? : 0 ; //clear condition; //q+ is the new output value 1 1 0 : ? : 1 ; //latch q = data = 1 0 1 0 : ? : 0 ; //latch q = data = 0 ? 0 0 : ? : - ; //retain original state if clock = 0 endtable endprimitive Sequential UDPs can include the reg declaration in the port list using an ANSI C style UDP declaration. They can also initialize the value of the output in the port declaration. Example 12-8 shows an example of an ANSI C style declaration for sequential UDPs. Example 12-8 ANSI C Style Port Declaration for Sequential UDP //Define level-sensitive latch by using UDP. primitive latch(output reg q = 0, input d, clock, clear); -- --
  3. -- endprimitive 12.3.2 Edge-Sensitive Sequential UDPs Edge-sensitive sequential UDPs change state based on edge transitions and/or input levels. Edge-triggered flipflops are the most common example of edge- sensitive sequential UDPs. Consider the negative edge-triggered D-flipflop with clear shown in Figure 12-4. Figure 12-4. Edge-Sensitive D-flipflop with clear In the edge-sensitive flipflop shown above, if clear =1, the output q is always 0. If clear = 0, the D-flipflop functions normally. On the negative edge of clock, i.e., transition from 1 to 0, q gets the value of d. If clock transitions to an unknown state or on a positive edge of clock, do not change the value of q. Also, if d changes when clock is steady, hold value of q. The Verilog UDP description for the D-flipflop is shown in Example 12-9. Example 12-9 Negative Edge-Triggered D-flipflop with clear //Define an edge-sensitive sequential UDP; primitive edge_dff(output reg q = 0, input d, clock, clear); table // d clock clear : q : q+ ; ? ? 1 : ? : 0 ; //output = 0 if clear = 1 ? ? (10): ? : - ; //ignore negative transition of clear 1 (10) 0 : ? : 1 ; //latch data on negative transition of 0 (10) 0 : ? : 0 ; //clock ? (1x) 0 : ? : - ; //hold q if clock transitions to unknown //state
  4. ? (0?) 0 : ? : - ; //ignore positive transitions of clock ? (x1) 0 : ? : - ; //ignore positive transitions of clock (??) ? 0 : ? : - ; //ignore any change in d when clock //is steady endtable endprimitive In Example 12-9, edge transitions are explained as follows: • (10) denotes a negative edge transition from logic 1 to logic 0. • (1x) denotes a transition from logic 1 to unknown x state. • (0?) denotes a transition from 0 to 0, 1, or x. Potential positive-edge transition. • (??) denotes any transition in signal value 0,1, or x to 0, 1, or x. It is important to completely specify the UDP by covering all possible combinations of transitions and levels in the state table for which the outputs have a known value. Otherwise, some combinations may result in an unknown value. Only one edge specification is allowed per table entry. More than one edge specification in a single table entry, as shown below, is illegal in Verilog. table ... (01) (10) 0 : ? : 1 ; //illegal; two edge transitions in an entry ... endtable 12.3.3 Example of a Sequential UDP We discussed small examples of sequential UDPs. Let now describe a slightly bigger example, a 4-bit binary ripple counter. A 4-bit binary ripple counter was designed with T-flipflops in Section 6.5.3, Ripple Counter. The T-flipflops were built with negative edge-triggered D-flipflops. Instead, let us define the T-flipflop directly as a UDP primitive. The UDP definition for the T-flipflop is shown in Example 12-10. Example 12-10 T-Flipflop with UDP
  5. // Edge-triggered T-flipflop primitive T_FF(output reg q, input clk, clear); //no initialization of q; TFF will be initialized with clear signal table // clk clear : q : q+ ; //asynchronous clear condition ? 1 : ? :0; //ignore negative edge of clear ? (10) : ? : - ; //toggle flipflop at negative edge of clk (10) 0 : 1 : 0 ; (10) 0 : 0 : 1 ; //ignore positive edge of clk (0?) 0 : ? : - ; endtable endprimitive To build the ripple counter with T-flipflops, four T-flipflops are instantiated in the ripple counter, as shown in Example 12-11. Example 12-11 Instantiation of T_FF UDP in Ripple Counter // Ripple counter module counter(Q , clock, clear); // I/O ports output [3:0] Q; input clock, clear; // Instantiate the T flipflops // Instance names are optional T_FF tff0(Q[0], clock, clear); T_FF tff1(Q[1], Q[0], clear); T_FF tff2(Q[2], Q[1], clear);
  6. T_FF tff3(Q[3], Q[2], clear); endmodule If stimulus shown in Example 6-9 on page 113 is applied to the counter, identical simulation output will be obtained.  
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