Standard Sequential Components Tutorial part 2

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Standard Sequential Components Tutorial part 2

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Appendix C − MAX+plus II Tutorial 2 Page 1 of 11 Contents Contents

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  1. Appendix C − MAX+plus II Tutorial 2 Page 1 of 11 Contents Contents ........................................................................................................................................................................ 1 Appendix C MAX+plus II Tutorial 2 .................................................................................................................... 2 C.1 Getting Started .............................................................................................................................................. 2 C.1.1 Preparing a Folder for the Project ......................................................................................................... 2 C.1.2 Creating a Project.................................................................................................................................. 2 C.1.3 Editing the VHDL Source Code............................................................................................................ 2 C.2 Synthesis for Programming the PLD............................................................................................................. 3 C.3 Circuit Simulation ......................................................................................................................................... 3 C.4 Using the Floorplan Editor............................................................................................................................ 5 C.4.1 Selecting the Target Device .................................................................................................................. 5 C.4.2 Maping the I/O Pins with the Floorplan Editor ..................................................................................... 6 C.5 Fitting the Netlist and Pins to the PLD.......................................................................................................... 7 C.6 Programming the FPGA................................................................................................................................ 8 C.6.1 Connecting and Configuring the UP2 Board......................................................................................... 8 C.6.2 Configure the ByteBlaster Cable........................................................................................................... 9 C.6.3 Selecting the File to Program .............................................................................................................. 10 C.6.4 Programming the PLD ........................................................................................................................ 11 C.7 Testing the Hardware .................................................................................................................................. 11 Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  2. Appendix C − MAX+plus II Tutorial 2 Page 2 of 11 Appendix C MAX+plus II Tutorial 2 In tutorial 1, we saw how a VHDL description of a 4-bit counter circuit is synthesized and simulated in MAX+plus II. Test values for the input signals Clock and Reset were manually setup in the simulator. In order for the synthesized circuit to operate in hardware, these input signals must be provided for by the hardware. For example, the Reset signal must be connected to an input switch, and a clock generator is needed for the Clock signal. Furthermore, the counter output signal Q must be connected to LEDs in order for us to see that the counter is really working. In this tutorial, we will expand on the counter circuit by adding a clock generator, and a 7-segment decoder. The UP2 development board already has a built in clock source running at a frequency of approximately 25MHz. The clock generator circuit simply divides this clock speed down to 1Hz. The 7-segment decoder converts the 4-bit counter output to drive a 7-segment LED display. An enclosing entity, top, is used to connect these three entities (clockdiv, counter, and decoder) together to form one complete circuit. This circuit is then downloaded to the PLD on the UP2 development board, and after applying power, you can actually see the count being displayed on the 7- segment LED. C.1 Getting Started C.1.1 Preparing a Folder for the Project 1. Use Windows File Manager to create a new folder for this project. This tutorial uses the folder called topcounter in the root directory of the C drive. 2. The VHDL source code for the four entities, top, clockdiv, counter, and decoder, can be found on the accompanying CD-ROM in the four files top.vhd, clockdiv.vhd, counter.vhd, and decoder.vhd located in the directory :\VHDL Examples\Appendix C\topcounter. Using Windows File Manager, copy these four files to the new folder c:\topcounter that you have created in step 1. 3. Start MAX+plus II if it is not already started. If there are windows opened from a previous session, you can close them. C.1.2 Creating a Project 1. From the Manager window menu, select File | Project | Name, or simply click on the icon . 2. Select the C drive from the Drives dropdown list. 3. Select the topcounter directory on the C drive. You should see the file top.vhd listed in the Files box. 4. Select the file top.vhd. The filename will be copied to the Project Name text field. 5. Click OK. The MAX+plus II Manager window title should now show c:\topcounter\top. C.1.3 Editing the VHDL Source Code • From the Manager window menu, select File | Hierarchy Project Top, or click on the icon to open the top entity VHDL source code top.vhd. The entity name for this circuit is top. The top entity name for the project must be the same as the project name, and the file name. • Use File | Open from the Manager window menu to open the other three VHDL source files for viewing. You can use this text editor to modify the code if necessary. For now, we will not make any modifications. Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  3. Appendix C − MAX+plus II Tutorial 2 Page 3 of 11 C.2 Synthesis for Programming the PLD 1. From the Manager window menu, select MAX+plus II | Compiler, or click on the icon to bring up the Compiler window. 2. From the Compiler window menu, that is, with the Compiler window selected as the active window, select Processing | Functional SNF Extractor so that there is no check mark next to it. The compiler window for full synthesis should look like Figure C-1. Figure C-1. Compiler window for full synthesis. 3. From the Compiler window menu, select Processing | Smart Recompile. With this option turned on, if you change any pin assignments and re-compile, the compiler does not have to perform a full synthesis. 4. Click on the Start button to start the synthesis. You will then see the progress of the synthesis. 5. At the end of the synthesis, if there are no syntax errors, you will see a message window saying that the compilation was successful. Click OK to close the message window. C.3 Circuit Simulation The following steps for circuit simulation in this section are only necessary if you want to perform a simulation of the circuit. In practice, it is advisable to simulate the circuit to make sure that it is correct before implementing it on a PLD. For this tutorial, you can skip this step, and go directly to Section 0 for programming the PLD. 1. From the Manager window menu, select MAX+plus II | Waveform Editor. 2. From the Waveform Editor window menu, select Node | Enter Nodes from SNF. You can also right click under the Name section in the Waveform Editor window, and select Enter Nodes from SNF from the pop-up menu. You will see something similar to the Enter Nodes from SNF window shown in Figure C-2. Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  4. Appendix C − MAX+plus II Tutorial 2 Page 4 of 11 Figure C-2. Window for adding signals for simulation. 3. Click on the List button, and a list of available nodes and groups will be displayed in the Available Nodes & Groups box. 4. Select the signals that you want to see in the simulation trace, and then click on the => button. The signals that we want are: ResetN, ClockSource, a, b, c, d, e, f, and g. The signals a to g are the signals for driving the seven LEDs on the 7-segment LED. After clicking on the => button, the selected signals will be moved to the Selected Nodes & Groups box. For this particular circuit, you may have a slight problem with the simulation, because the signal ClockSource is assumed to be running at 25MHz, and the Clockdiv circuit divides the clock down from 25MHz to 1Hz. So to even see a few counts, you will need the simulation end time to be very large. Two possible solutions to make the simulation work are to remove the Clockdiv entity from the circuit, or modify the clock divide VHDL code so that it does not divide the clock. 5. Click on OK when you are finished. The selected signals will now be inserted in the Waveform Editor window. 6. Select File | End Time from the Waveform Editor window menu to set the simulation end time to 10us. Note that 10us is still too small as pointed out in the note in step 4. 7. Assign values to the ClockSource signal using the button. 8. Assign a logic 1 value to the ResetN signal using the button. 9. Save the Waveform Editor window file as top.scf. 10. From the Manager window menu, select MAX+plus II | Simulator, or click on the icon to bring up the Simulator window to start the simulation of the design. 11. Click on the Open SCF button to view the simulation result in the Waveform Editor window as shown in Figure C-3. Notice in the waveform that at 9us, the count is still at 0 as shown by the seven segment signals. For these Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  5. Appendix C − MAX+plus II Tutorial 2 Page 5 of 11 seven signals, a 0 turns on the LED and a 1 turns it off as shown in Figure C-4. Figure C-3. Resulting waveform after the simulation for 10us. a f b g e c d Figure C-4. Segment placements of the 7-segment LED. C.4 Using the Floorplan Editor Since we want to download the circuit to a PLD, we need to specify what the target device is, and map the I/O signals to the actual pins on the PLD. C.4.1 Selecting the Target Device 1. Open the Device selection window by selecting Assign | Device from the Manager window menu as shown in Figure C-5. Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  6. Appendix C − MAX+plus II Tutorial 2 Page 6 of 11 Figure C-5. Selecting the 10K70RC240-4 PLD chip. 2. Remove the checkmark from Show Only Fastest Speed Grades. 3. In the Device Family dropdown box, select FLEX10K. 4. In the Devices list, select EPF10K70RC240-4. This is the larger one of the two PLD devices that is on the UP2 board. 5. Click on OK. 6. Put a checkmark for Maintain Current Synthesis Regardless of Device or Speed Grade Changes. C.4.2 Maping the I/O Pins with the Floorplan Editor 1. We also need to specify which physical pins on the chip will be assigned to the I/O signals for the circuit. From the Manager window menu, select MAX+plus II | Floorplan Editor, or click on the icon to bring up the Floorplan Editor window. 2. From the Floorplan Editor window menu, select Layout | Device View. You should see a physical layout of the pins for the selected PLD chip as shown in Figure C-6. You may have to scroll the window or zoom out to see the pins. All the pins are labeled with a pin number, and the name of the signal that it is assigned to. Pins in blue are already assigned to a signal. In the figure, the signal ClockSource is already assigned to pin 91. All the pins in white are currently unassigned, and available to use. Signals from the circuit that have not yet been assigned to any pins are listed in the top right box labeled Unassigned Nodes & Pins. Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  7. Appendix C − MAX+plus II Tutorial 2 Page 7 of 11 Figure C-6. The Floorplan Editor showing the 10K70RC240-4 chip pins, and the signal names for the circuit. 3. From the Floorplan Editor window menu, select Layout | Current Assignments Floorplan, or click on the icon in the toolbar on the left. 4. To assign a signal to a pin, simply drag the icon or next to the signal from the Unassigned Nodes & Pins list to one of the white pins in the floorplan. The pin color changes to blue when a signal is assigned to it. Perform the following signal to pin assignments: Signal Pin Number Comment ClockSource 91 Pin 91 is connected to the built-in 25MHz clock source ResetN 29 Pine 29 is connected to pushbutton switch FLEX_PB2 a 17 Pin 17 is connected to segment a on digit 2 of the 7-segment LEDs b 18 Pin 18 is connected to segment b on digit 2 of the 7-segment LEDs c 19 Pin 19 is connected to segment c on digit 2 of the 7-segment LEDs d 20 Pin 20 is connected to segment d on digit 2 of the 7-segment LEDs e 21 Pin 21 is connected to segment e on digit 2 of the 7-segment LEDs f 23 Pin 23 is connected to segment f on digit 2 of the 7-segment LEDs g 24 Pin 24 is connected to segment g on digit 2 of the 7-segment LEDs • You can change a pin assignment by dragging the signal to another pin, or back to the signal list box. C.5 Fitting the Netlist and Pins to the PLD We need to compile the topcounter circuit again for fitting the netlist and pins to the selected PLD. If you have selected Processing | Smart Recompile in step C.2, then this step would be faster, since the compiler does not Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  8. Appendix C − MAX+plus II Tutorial 2 Page 8 of 11 have to re-synthesize the circuit. 1. Bring up the Compiler window by selecting MAX+plus II | Compiler from the Manager window menu, or click on the icon . 2. From the Compiler window menu, select Processing | Functional SNF Extractor so that there is no check mark next to it. The compiler window for full synthesis should look like Figure C-7. Figure C-7. Compiler window for full synthesis. 3. Click on the Start button to start the compilation. 4. At the end of the synthesis, if there are no syntax errors, you will see a message window saying that the compilation was successful. Click OK to close the message window. C.6 Programming the FPGA C.6.1 Connecting and Configuring the UP2 Board 1. Attach the ByteBlaster parallel cable directly to the PC’s parallel port and the JTAG_IN connector on the UP2 development board as shown in Figure C-8. Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  9. Appendix C − MAX+plus II Tutorial 2 Page 9 of 11 9v in JTAG_IN JTAG jumpers 7-segment LED pushbutton switch EPF10K70 PLD Figure C-8. UP2 development board. 2. Set the JTAG jumpers, TDI, TDO, DEVICE, and BOARD, on the development board as follows: TDI TDO DEVICE BOARD C1 C1 C1 C1 C2 C2 C2 C2 C3 C3 C3 C3 3. Plug in the 9V power for the board. C.6.2 Configure the ByteBlaster Cable 1. Select MAX+plusII | Programmer from the Manager window menu, or click on the icon to bring up the Programmer window similar to the one shown in Figure C-9. Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  10. Appendix C − MAX+plus II Tutorial 2 Page 10 of 11 Figure C-9. Programmer window. 2. From the Programmer window menu, select Options | Hardware Setup. 3. Select ByteBlaster(MV) from the Hardware Type dropdown list. If this is not available, then the device driver has not been installed. Follow the instructions for installing the device driver for the ByteBlaster in the UP2 User Guide. 4. Select the correct parallel port (usually LPT1). 5. Click OK. C.6.3 Selecting the File to Program 1. From the Programmer window menu, select JTAG | Multi-Device JTAG Chain as shown in Figure C-10. If you have previously selected a file, and wants to program with another file, you need to select Multi-Device JTAG Chain Setup instead. Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
  11. Appendix C − MAX+plus II Tutorial 2 Page 11 of 11 Figure C-10. Device and file selection window. 2. Select EPF10K70 from the Device Name dropdown list. 3. Click on the Select Programming File button. 4. Select the file top.sof, and click OK. 5. Click Add to add the device and file to the Device Names and Programming File Names box. 6. Click the Detect JTAG Chain Info button. 7. If everything is setup correctly, you should see the message “JTAG chain information confirmed by hardware check.” Click OK to close the message window. 8. Click OK to close the Multi-Device JTAG Chain Setup window. 9. If you get the message “Do you want to switch to the multi-device JTAG chain mode?” then click Yes. C.6.4 Programming the PLD 1. In the Programmer window as shown in Figure C-9, click on the Configure button to start the configuration (programming). 2. At the end of the programming, you will see a message window saying that the configuration is complete. Click OK to close the message window. C.7 Testing the Hardware 1. You should see the counter counts on the 7-segment LED. When you press the pushbutton, the counter resets to zero. Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
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