VHDL

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VHDL

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Ngôn ngữ VHDL cho người mới bắt đầu, VHDL là ngôn ngữ dùng để mô tả các hệ thống điện tử số và được sử dụng trong quá trình thiết kế.

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  1. Appendix A − VHDL Summary Page 1 of 22 Contents Contents ........................................................................................................................................................................ 1 Appendix A VHDL Summary ............................................................................................................................... 2 A.1 Basic Language Elements ............................................................................................................................. 2 A.1.1 Comments ............................................................................................................................................. 2 A.1.2 Identifiers .............................................................................................................................................. 2 A.1.3 Data Objects.......................................................................................................................................... 2 A.1.4 Data Types ............................................................................................................................................ 2 A.1.5 Data Operators ...................................................................................................................................... 5 A.1.6 ENTITY ................................................................................................................................................ 5 A.1.7 ARCHITECTURE ................................................................................................................................ 6 A.1.8 GENERIC ............................................................................................................................................. 7 A.1.9 PACKAGE............................................................................................................................................ 8 A.2 Dataflow Model Concurrent Statements ....................................................................................................... 9 A.2.1 Concurrent Signal Assignment.............................................................................................................. 9 A.2.2 Conditional Signal Assignment........................................................................................................... 10 A.2.3 Selected Signal Assignment ................................................................................................................ 10 A.2.4 Dataflow Model Example ................................................................................................................... 11 A.3 Behavioral Model Sequential Statements.................................................................................................... 11 A.3.1 PROCESS ........................................................................................................................................... 11 A.3.2 Sequential Signal Assignment............................................................................................................. 11 A.3.3 Variable Assignment ........................................................................................................................... 12 A.3.4 WAIT .................................................................................................................................................. 12 A.3.5 IF THEN ELSE ................................................................................................................................... 12 A.3.6 CASE .................................................................................................................................................. 13 A.3.7 NULL .................................................................................................................................................. 13 A.3.8 FOR..................................................................................................................................................... 13 A.3.9 WHILE................................................................................................................................................ 14 A.3.10 LOOP .................................................................................................................................................. 14 A.3.11 EXIT ................................................................................................................................................... 14 A.3.12 NEXT .................................................................................................................................................. 14 A.3.13 FUNCTION ........................................................................................................................................ 15 A.3.14 PROCEDURE ..................................................................................................................................... 15 A.3.15 Behavioral Model Example................................................................................................................. 16 A.4 Structural Model Statements ....................................................................................................................... 17 A.4.1 COMPONENT Declaration ................................................................................................................ 17 A.4.2 PORT MAP......................................................................................................................................... 17 A.4.3 OPEN .................................................................................................................................................. 18 A.4.4 GENERATE........................................................................................................................................ 18 A.4.5 Structural Model Example .................................................................................................................. 18 A.5 Conversion Routines ................................................................................................................................... 20 A.5.1 CONV_INTEGER()............................................................................................................................ 20 A.5.2 CONV_STD_LOGIC_VECTOR(,) .................................................................................................... 20 Index ....................................................................................................................................................................... 21 Principles of Digital Logic Design Enoch Hwang Last updated 11/20/2003 4:55 PM
  2. Appendix A − VHDL Summary Page 2 of 22 Appendix A VHDL Summary VHDL is a hardware description language for modeling digital circuits that can range from simple connection of gates to complex systems. VHDL is an acronym for VHSIC Hardware Description Language, and VHSIC in turn is an acronym for Very High Speed Integrated Circuits. This appendix gives a brief summary of the basic VHDL elements and its syntax. Many advance features of the language are omitted. Interested readers should refer to other references for detail coverage. A.1 Basic Language Elements A.1.1 Comments Comments are preceded by two consecutive hyphens ( -- ) and are terminated at the end of the line. Example: -- This is a comment A.1.2 Identifiers VHDL identifier syntax: • A sequence of one or more upper case letters, lower case letters, digits, and the underscore. • Upper and lower case letters are treated the same, i.e. case insensitive. • The first character must be a letter. • The last character cannot be the underscore. • Two underscores cannot be together. A.1.3 Data Objects There are three kinds of data objects: signals, variables, and constants. The data object SIGNAL represents logic signals on a wire in the circuit. A signal does not have memory, thus, if the source of the signal is removed, the signal will not have a value. A VARIABLE object remembers its content and is used for computations in a behavioral model. A CONSTANT object must be initialized with a value when declared and this value cannot be changed. Example: SIGNAL x: BIT; VARIABLE y: INTEGER; CONSTANT one: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; A.1.4 Data Types BIT and BIT_VECTOR The BIT and BIT_VECTOR types are predefined in VHDL. Objects of these types can have the values ‘0’ or ‘1’. The BIT_VECTOR type is simply a vector of type BIT. A vector with all bits having the same value can be obtained using the OTHERS keyword. Example: SIGNAL x: BIT; SIGNAL y: BIT_VECTOR(7 DOWNTO 0); Principles of Digital Logic Design Enoch Hwang Last updated 11/20/2003 4:55 PM
  3. Appendix A − VHDL Summary Page 3 of 22 x
  4. Appendix A − VHDL Summary Page 4 of 22 INTEGER The predefined INTEGER type defines binary number objects for use with arithmetic operators. By default, an INTEGER signal uses 32 bits to represent a signed number. Integers using fewer bits can also be declared with the RANGE keyword. Example: SIGNAL x: INTEGER; SIGNAL y: INTEGER RANGE –64 to 64; BOOLEAN The predefined BOOLEAN type defines objects having the two values TRUE and FALSE. Example: SIGNAL x: BOOLEAN; Enumeration TYPE An enumeration type allows the user to specify the values that the data object can have. Syntax: TYPE identifier IS (value1, value2, … ); Example: TYPE state_type IS (S1, S2, S3); SIGNAL state: state_type; state
  5. Appendix A − VHDL Summary Page 5 of 22 SUBTYPE cell IS STD_LOGIC_VECTOR(3 DOWNTO 0); TYPE memArray IS ARRAY(0 TO 15) OF cell; Some standard subtypes include: • NATURAL – an integer in the range 0 to INTEGER'HIGH. • POSITIVE – an integer in the range 1 to INTEGER'HIGH. A.1.5 Data Operators The VHDL Built-in operators are listed below. Logical Operators Operation Example AND and a AND b OR or a OR b NOT not NOT a NAND nand a NAND b NOR nor a NOR b XOR xor a XOR b XNOR xnor a XNOR b Arithmetic Operators + addition a+b – subtraction a–b * multiplication a*b / division a/b MOD modulus a MOD b REM remainder a REM b ** exponentiation a ** 2 & concatenation 'a' & 'b' ABS absolute Relational Operators = equal /= not equal < less than greater than >= greater than or equal Shift Operators sll shift left logical srl shift right logical sla shift left arithmetic sra shift right arithmetic rol rotate left ror rotate right A.1.6 ENTITY An ENTITY declaration declares the external or user interface of the module similar to the declaration of a function. It specifies the name of the entity and its interface. The interface consists of the signals to be passed into the entity, or out from it. Principles of Digital Logic Design Enoch Hwang Last updated 11/20/2003 4:55 PM
  6. Appendix A − VHDL Summary Page 6 of 22 Syntax: ENTITY entity-name IS PORT (list-of-port-names-and-types); END entity-name; Example: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Siren IS PORT ( M: IN STD_LOGIC; D: IN STD_LOGIC; V: IN STD_LOGIC; S: OUT STD_LOGIC); END Siren; A.1.7 ARCHITECTURE The ARCHITECTURE body defines the actual implementation of the functionality of the entity. This is similar to the definition or implementation of a function. The syntax for the architecture varies depending on the model (dataflow, behavioral, or structural) you use. Syntax for dataflow model:: ARCHITECTURE architecture-name OF entity-name IS signal-declarations; BEGIN concurrent-statements; END architecture-name; The concurrent-statements are executed concurrently. Example: ARCHITECTURE Siren_Dataflow OF Siren IS SIGNAL term_1: STD_LOGIC; BEGIN term_1
  7. Appendix A − VHDL Summary Page 7 of 22 ARCHITECTURE Siren_Behavioral OF Siren IS SIGNAL term_1: STD_LOGIC; BEGIN PROCESS (D, V, M) BEGIN term_1
  8. Appendix A − VHDL Summary Page 8 of 22 GENERIC (n: INTEGER := 4); PORT ( -- the vector size is 4 since n is 4 A, B: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); Cout: OUT STD_LOGIC; SUM: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); S: OUT STD_LOGIC); END Siren; A.1.9 PACKAGE A PACKAGE provides a mechanism to group together and share declarations that are used by several entity units. A package itself includes a declaration and, optionally, a body. The package declaration and body are usually stored together in a separate file from the rest of the design units. The file name given for this file must be the same as the package name. In order for the complete design to synthesize correctly using MAX+PLUS II, you must first synthesize the package as a separate unit. After that you can synthesize the unit that uses that package. PACKAGE Declaration and Body The PACKAGE declaration contains declarations that may be shared between different entity units. It provides the interface, that is, items that are visible to the other entity units. The optional PACKAGE BODY contains the implementations of the functions and procedures that are declared in the PACKAGE declaration. Syntax for PACKAGE declaration: PACKAGE package-name IS type-declarations; subtype-declarations; signal-declarations; variable-declarations; constant-declarations; component-declarations; function-declarations; procedure-declarations; END package-name; Syntax for PACKAGE body: PACKAGE BODY package-name IS function-definitions; -- for functions declared in the package declaration procedure-definitions; -- for procedures declared in the package declaration END package-name; Example: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; PACKAGE my_package IS SUBTYPE bit4 IS STD_LOGIC_VECTOR(3 DOWNTO 0); FUNCTION Shiftright (input: IN bit4) RETURN bit4; -- declare a function SIGNAL mysignal: bit4; -- a global signal END my_package; PACKAGE BODY my_package IS -- implementation of the Shiftright function FUNCTION Shiftright (input: IN bit4) RETURN bit4 IS Principles of Digital Logic Design Enoch Hwang Last updated 11/20/2003 4:55 PM
  9. Appendix A − VHDL Summary Page 9 of 22 BEGIN RETURN '0' & input(3 DOWNTO 1); END shiftright; END my_package; Using a PACKAGE To use a package, you simply include a LIBRARY and USE statement for that package. Before synthesizing the module that uses the package, you need to first synthesize the package by itself as a top-level entity. Syntax: LIBRARY WORK; USE WORK.package-name.ALL; Example: LIBRARY WORK; USE WORK.my_package.ALL; ENTITY test_package IS PORT ( x: IN bit4; z: OUT bit4); END test_package; ARCHITECTURE Behavioral OF test_package IS BEGIN mysignal
  10. Appendix A − VHDL Summary Page 10 of 22 A.2.2 Conditional Signal Assignment Selects one of several different values to assign to a signal based on different conditions. This statement is executed whenever a signal in any one of the value or condition changes. Syntax: signal
  11. Appendix A − VHDL Summary Page 11 of 22 A.2.4 Dataflow Model Example -- outputs a 1 if the 4-bit input is a prime number, 0 otherwise LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Prime IS PORT ( number: IN STD_LOGIC_VECTOR(3 DOWNTO 0); yes: OUT STD_LOGIC); END Prime; ARCHITECTURE Prime_Dataflow OF Prime IS BEGIN WITH number SELECT yes
  12. Appendix A − VHDL Summary Page 12 of 22 Syntax: signal
  13. Appendix A − VHDL Summary Page 13 of 22 sequential-statements2; … ELSE sequential-statements3; END IF; Example: IF count /= 10 THEN -- not equal count := count + 1; ELSE count := 0; END IF; A.3.6 CASE Syntax: CASE expression IS WHEN choices => sequential-statements; WHEN choices => sequential-statements; … WHEN OTHERS => sequential-statements; END CASE; Example: CASE sel IS WHEN "00" => z z z z
  14. Appendix A − VHDL Summary Page 14 of 22 sum := 0; FOR count IN 1 TO 10 LOOP sum := sum + count; END LOOP; A.3.9 WHILE6 Syntax: WHILE condition LOOP sequential-statements; END LOOP; A.3.10 LOOP4 Syntax: LOOP sequential-statements; EXIT WHEN condition; END LOOP; A.3.11 EXIT4 The EXIT statement can only be used inside a loop. It causes execution to jump out of the innermost loop and is usually used in conjunction with the LOOP statement. Syntax: EXIT WHEN condition; A.3.12 NEXT The NEXT statement can only be used inside a loop. It causes execution to skip to the end of the current iteration and continue with the beginning of the next iteration. It is usually used in conjunction with the FOR statement. Syntax: NEXT WHEN condition; Example: sum := 0; FOR count IN 1 TO 10 LOOP NEXT WHEN count = 3; sum := sum + count; END LOOP; 6 Not supported by MAX+ plus II. Principles of Digital Logic Design Enoch Hwang Last updated 11/20/2003 4:55 PM
  15. Appendix A − VHDL Summary Page 15 of 22 A.3.13 FUNCTION Syntax for function declaration: FUNCTION function-name (parameter-list) RETURN return-type; Syntax for function definition: FUNCTION function-name (parameter-list) RETURN return-type IS BEGIN sequential-statements; END function-name; Syntax for function call: function-name (actuals); Parameters in the parameter-list can be either signals or variables of mode IN only. Example: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY test_function IS PORT ( x: IN STD_LOGIC_VECTOR(3 DOWNTO 0); z: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END test_function; ARCHITECTURE Behavioral OF test_function IS SUBTYPE bit4 IS STD_LOGIC_VECTOR(3 DOWNTO 0); FUNCTION Shiftright (input: IN bit4) RETURN bit4 IS BEGIN RETURN '0' & input(3 DOWNTO 1); END shiftright; SIGNAL mysignal: bit4; BEGIN PROCESS BEGIN mysignal
  16. Appendix A − VHDL Summary Page 16 of 22 Syntax for procedure call: procedure -name (actuals); Parameters in the parameter-list are variables of modes IN, OUT, or INOUT. Example: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY test_procedure IS PORT ( x: IN STD_LOGIC_VECTOR(3 DOWNTO 0); z: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END test_procedure; ARCHITECTURE Behavioral OF test_procedure IS SUBTYPE bit4 IS STD_LOGIC_VECTOR(3 DOWNTO 0); PROCEDURE Shiftright (input: IN bit4; output: OUT bit4) IS BEGIN output := '0' & input(3 DOWNTO 1); END shiftright; BEGIN PROCESS VARIABLE mysignal: bit4; BEGIN Shiftright(x, mysignal); z Segs Segs Segs Segs Segs Segs Segs Segs
  17. Appendix A − VHDL Summary Page 17 of 22 WHEN "1000" => Segs Segs Segs c1, si=>s0, cin=>c0, xi=>x0, yi=>y0); U2: half_adder PORT MAP (cin=>c1, xi=>x1, yi=>y1, cout=>c2, si=>s1); Principles of Digital Logic Design Enoch Hwang Last updated 11/20/2003 4:55 PM
  18. Appendix A − VHDL Summary Page 18 of 22 A.4.3 OPEN The OPEN keyword is used in the PORT MAP association-list to signify that that particular port is not connected or used. Example: U1: half_adder PORT MAP (x0, y0, c0, OPEN, s0); A.4.4 GENERATE The GENERATE statement works like a macro expansion. It provides a simple way to duplicate similar components. Syntax: label: FOR identifier IN start [TO | DOWNTO] stop GENERATE port-map-statements; END GENERATE label; Example: -- using a FOR-GENERATE statement to generate four instances of the full adder -- component for a 4-bit adder LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Adder4 IS PORT ( Cin: IN STD_LOGIC; A, B: IN STD_LOGIC_VECTOR(3 DOWNTO 0); Cout: OUT STD_LOGIC; SUM: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END Adder4; ARCHITECTURE Structural OF Adder4 IS COMPONENT FA PORT ( ci, xi, yi: IN STD_LOGIC; co, si: OUT STD_LOGIC); END COMPONENT; SIGNAL Carryv: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN Carryv(0)
  19. Appendix A − VHDL Summary Page 19 of 22 D V S M -- declare and define the 2-input OR gate LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY myOR IS PORT ( in1, in2: IN STD_LOGIC; out1: OUT STD_LOGIC); END myOR; ARCHITECTURE OR_Dataflow OF myOR IS BEGIN out1
  20. Appendix A − VHDL Summary Page 20 of 22 -- with the input to the AND gate SIGNAL term1: STD_LOGIC; BEGIN U0: myOR PORT MAP (D, V, term1); U1: myAND PORT MAP (term1, M, S); END Siren_Structural; A.5 Conversion Routines A.5.1 CONV_INTEGER() Converts a std_logic_vector type to an integer; Requires: LIBRARY IEEE; USE IEEE.STD_LOGIC_UNSIGNED.ALL; Syntax: CONV_INTEGER(std_logic_vector) Example: LIBRARY IEEE; USE IEEE.STD_LOGIC_UNSIGNED.ALL; SIGNAL four_bit: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL n: INTEGER; n := CONV_INTEGER(four_bit); A.5.2 CONV_STD_LOGIC_VECTOR(,) Converts an integer type to a std_logic_vector type. Requires: LIBRARY IEEE; USE IEEE.STD_LOGIC_ARITH.ALL; Syntax: CONV_STD_LOGIC_VECTOR (integer, number_of_bits) Example: LIBRARY IEEE; USE IEEE.STD_LOGIC_ARITH.ALL; SIGNAL four_bit: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL n: INTEGER; four_bit := CONV_STD_LOGIC_VECTOR(n, 4); Principles of Digital Logic Design Enoch Hwang Last updated 11/20/2003 4:55 PM
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