The research of optimal condition for etching silicon in TMAH solution with controlled etch rate and low surface roughness is the purpose of this study. The investigation on the influence of temperature, agitation, size of etch-window, etch time on etch rate and the surface roughness were carried out. With the TMAH concentration of 20% in weight, the optimal etching conditions were as follows: temperature of about 80 – 90 oC, agitation of 150 - 200 rpm. The etch rate is controlled in range of 0.49 – 0.72 µm/min. ...
Many people in the field of microelectromechanical systems (MEMS) share the belief that a revolution is under way. As
MEMS begin to permeate more and more industrial procedures, not only engineering but society as a whole will be strongly
affected. MEMS provide a new design technology that could rival, and perhaps even surpass, the societal impact of integrated
circuits (ICs). Is this fact or fiction? If it is fact, then several questions must be asked.
Making microsystems at a scale level of few microns is called micromachining.
Micromachining is used to fabricate three-dimensional microstructures. It is the
foundation of a technology called Micro-Electro-Mechanical-Systems (MEMS). MEMS
usually consist of three major parts: sensors, actuators, and an associate electronic
circuitry that acts as the brain and controller of the whole system.
This book is designed for a one-semester course on Nano- and
Microelectromechanical Systems or Nano- and Microengineering. A typical
background needed includes calculus, electromagnetics, and physics. The
purpose of this book is to bring together in one place the various methods,
techniques, and technologies that students and engineers need in solving a
wide array of engineering problems in formulation, modeling, analysis,
design, and optimization of high-performance microelectromechanical and
nanoelectromechanical systems (MEMS and NEMS).
Microelectromechanical systems are moving from the
simple single-function devices of the past to more elaborate
systems with complex structural intricacies with rich
dynamic subtleties. However, despite the relatively large
number of CAD for MEMS tools, products, and vendors,
MEMS design today still largely consists of working at the
whiteboard with colleagues and entering simplified equations
into Mathcad, if not writing them by hand on the back of an
envelope. Today’s CAD tools are useful for design
verification, but are not often used in the early phases of
The fundamental aim of microengineering — to take a design from a computer
aided design (CAD) software package and manifest it in a physical manner — may
be achieved through one of a number of different fabrication or micromachining
technologies. Many of these technologies employ a process known generally as
, or a variation of this process, to transfer a two-dimensional
pattern from a mask into the structural material.
The term “CMOS MEMS” most often describes pro-
cesses that create microstructures directly out of the metal/
dielectric interconnect stack in foundry CMOS. The metal-
lization and dielectric layers, normally used for electrical
interconnect, now serve a dual function as structural layers.
For example, the suspended n-well of Figure 3(d) is consid-
ered CMOS MEMS, since its beam suspension is made
from the CMOS interconnect stack.
There is significant motivation for making MEMS out
of CMOS. Leveraging foundry CMOS for MEMS is fast,
reliable, repeatable, and economical.
The first reported CMOS-MEMS processes produce
microstructural sidewalls by stacking the drain/source con-
tact cut and metal via cuts in the CMOS and removing the
metallization layers above the cuts . The substrate is
exposed in the cut regions. A wet or dry isotropic silicon
etch undercuts and releases the microstructures. Gaps
between microstructures are limited to several microns
because of artifacts in the etch pits from etching metal
above the CMOS contacts.
In the MEMS industry, systems for deep reactive-ion etching
(DRIE) utilize fast pumping, fast-response mass-flow controllers
inductive coupling of power, and heated chamber and pump lines
that are critical to achieve reliable etch rates. In contrast, we have
achieved 8:1 aspect-ratio PhC structures with 62nm vertica
membrane walls using a standard reactive-ion etching process based
on a sidewall passivation processes. In the remainder of this section
we discuss this fabrication process.