The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc.
Nowadays, embedded systems have permeated various aspects of industry. Therefore,
we can hardly discuss our life or society from now on without referring to embedded
systems. For wide-ranging embedded systems to continue their growth, a number of
high-quality fundamental and applied researches are indispensable.
This book addresses a wide spectrum of research topics on embedded systems,
including basic researches, theoretical studies, and practical work. The book consists of
This is the fourth version of the book and this version now not only provides
VHDL language coverage but design methodology information as well. This
version will guide the reader through the process of creating a VHDL
design, simulating the design, synthesizing the design, placing and routing
the design, using VITAL simulation to verify the final result, and a new
technique called At-Speed debugging that provides extremely fast design
verification. The design example in this version has been updated to reflect
the new focus on the design methodology....
In designing embedded systems, the exploration and synthesis of different design alternatives and co-verification of a specific implementation are the most demanding tasks. Kaffe, an open-source technology, provides a platform for building a runtime environment and integrating different design methodologies. Integrating Kaffe into embedded systems is the cornerstone of java-like technologies, allowing possibilities such as the development of portable programs on mobile devices.
The thesis includes four chapters together a conclusion in the last. Chapter 1 mentions about introduction that leads to motivation of this study. Chapter 2 presents the methodology related to multi scale analysis along with the code theories at different scale for RELAP5, CTF and Ansys CFX with focus on phase change models. The verification and assessment of modeling used in these codes versus experiment data are presented in chapter 3.