EURASIP Journal on Applied Signal Processing 2003:6, 530–542 c 2003 Hindawi Publishing Corporation
An FPGA Implementation of (3, 6)-Regular Low-Density Parity-Check Code Decoder
Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180, USA Email: email@example.com
Keshab K. Parhi
Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA Email: firstname.lastname@example.org.