Phc devices in soi

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  • Accordingly, PhC devices in SOI are realized by creating a lattice of air-holes in silicon, which can by achieved by anisotropic etching, of a high resolution patterned surface, into the silicon device layer (top layer of the SOI wafer). The refractive-index modulation, depth, and length of the device are the main parameters that are used to determine the optical properties of devices based on a photonic bandgap. Thus, stringent control of these parameters necessitates high-resolution lithography and high-aspect-ratio etching.

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  • To maximize the extent of the photonic bandgap in a finite-height photonic-crystal (PhC) slab one can increase the fill-factor in the PhC lattice. Among the realistic choices of possible 2D lattices, high fill- factor triangular lattices of cylindrical holes in a high index dielectric, namely silicon, are by far the most commonly used. In this paper, we present a method for fabrication of very high fill-factor PhC devices in silicon-on-insulator (SOI) substrates using electron-beam lithography and high-aspect-ratio reactive-ion etching (RIE).

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  • In the MEMS industry, systems for deep reactive-ion etching (DRIE) utilize fast pumping, fast-response mass-flow controllers inductive coupling of power, and heated chamber and pump lines that are critical to achieve reliable etch rates. In contrast, we have achieved 8:1 aspect-ratio PhC structures with 62nm vertica membrane walls using a standard reactive-ion etching process based on a sidewall passivation processes. In the remainder of this section we discuss this fabrication process.

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