Building a RISC System in an FPGA Part 2

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Building a RISC System in an FPGA Part 2

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introduced his plan to build a pipelined 16bit RISC processor and System-on-aChip in an FPGA. This month, he explores the CPU pipeline and designs the control unit. Listen up, because next month, he’ll tie it all together

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  1. Building a RISC System FEATURE ARTICLE in an FPGA Jan Gray Part 2: Pipeline and Control Unit Design In Part 1, Jan intro- l ast month, I discussed the instruction set and the datapath of an xr16 In the IF stage, it reads memory at the current PC address, captures the resulting instruction word in the instruction register IR, and incre- 16-bit RISC processor. Now, I’ll ments PC for the next cycle. In the duced his plan to explain how the control unit pushes DC stage, the instruction is decoded, the datapath’s buttons. and its operands are read from the build a pipelined 16- Figure 2 in Part 1 (Circuit Cellar, register file or extracted from an 116) showed the CTRL16 control unit immediate field in the IR. In the EX bit RISC processor schematic symbol in context. Inputs stage, the function units act upon the include the RDY signal from the operands. One result is driven through and System-on-a- memory controller, the next instruc- three-state buffers onto the result bus tion word INSN15:0 from memory, and and is written back into the register Chip in an FPGA. the zero, negative, carry, and overflow file as the cycle ends. outputs from the datapath. Consider executing a series of This month, he ex- The control unit outputs manage instructions, assume no memory wait the datapath. These outputs include states. In every pipeline cycle, fetch a plores the CPU pipe- pipeline control clock enables, new instruction and write back its register and operand selectors, ALU result two cycles later. You line and designs the controls, and result multiplexer simultaneously prepare the next output enables. Before designing the instruction address PC+2, fetch control unit. Listen up, control circuitry, first consider how the pipeline behaves in both good and because next month, bad times. t1 t2 t3 t4 t5 he’ll tie it all together. PIPELINED EXECUTION IF1 DC1 IF2 EX1 DC2 EX2 To increase instruction through- IF3 DC3 EX3 IF4 DC4 put, the xr16 has a three-stage pipeline—instruction fetch (IF), Table 1—Here the processor fetches instruction I1 at decode and operand fetch (DC), and time t1 and computes its result in t3, while I2 starts in t2 execute (EX). and ends in t4. Memory accesses are in boldface. CIRCUIT CELLAR® Issue 117 April 2000 1
  2. instruction IPC, decode instruction IPC-2, Listing 1—This C code produces assembly code that includes a load IL and a branch IB. Each causes and execute instruction IPC-4. pipeline headaches. Table 1 shows a normal pipelined execution of four instructions. That’s the simple case, but there are several if ((p->flags & 7) == 1) p->x = p->y; pipeline complications to consider— data hazards, memory wait states, I: lw r6,2(r10) ;load r6 with p->flags L load/store instructions, jumps and I: andi r6,7 ;is (p->flags & 7) 2 branches, interrupts, and direct I: addi r0,r6,-1 ;==1? 3 I: bne T memory access (DMA). B I: lw r6,6(r10) ;yes: load r6 with p->y What happens when an instruction 5 ... uses the result of the preceding instruction? I1: andi r1,7 hazards by swapping A and B operands, because neither EXL nor DC2 are I2: addi r2,r1,1 if possible, or inserting nops if not. finished at this point. In particular, DC2 must await the load result in Referring to time t3 of Table 1, EX1 MEMORY ACCESSES order to forward it to A, because I2 computes r1=r1&7, while DC2 fetches The processor has a single memory uses r6—the result of IL! the old value of r1. In t4, EX2 port for reading instructions and Finally, if (in t3) you don’t save the incorrectly adds 1 to this stale r1. loading and storing data. Most just-fetched I3 somewhere, you’ll lose This is a data hazard, and there are memory accesses are for fetching it, because in t4, the memory port is several ways to address it. The assem- instructions. The processor is also the busy with the load cycle. If you lose bler can reorder instructions or insert DMA engine, and a video refresh it, you’ll have to re-fetch it no sooner nops to avoid the problem. Or, the DMA cycle occurs once every eight than t5, with the result that even a no- control unit can detect the hazard and clocks or so. Therefore, in any given wait load requires three cycles, which stall the pipeline one cycle, in order clock cycle, the processor executes is unacceptable. to write-back the result to the register either an instruction fetch memory To fix this problem, the control file before fetching it as a source regis- cycle, a DMA memory cycle, or a unit has a 16-bit NEXTIR register and ter. However, these techniques hurt load/store memory cycle. an IR source multiplexer (IRMUX). In performance. Memory transactions are pipelined. t3, it captures I3 in NEXTIR, and then Instead, you do result forwarding, In each memory cycle, the processor in t4, IR is loaded from NEXTIR also known as register file bypass. drives the next memory cycle’s instead of from the memory port The datapath DC stage includes FWD, address and control signals and awaits (which is busy with the load). a 16-bit 2-1 multiplexer (mux) of RDY, indicating the access has been NEXTIR ensures a two-cycle load or AREG (register file port A), and the completed. So, what happens when store, at a cost of eight CLBs. result bus. Most of the time, FWD memory is not ready? As with instruction fetch accesses, passes AREG to the A operand regis- The simplest thing to do is to stop load/store memory accesses may ter, but when the control unit detects the pipeline for that cycle. CTRL have to wait on slow memory. For the hazard (DC source register equals deasserts all pipeline register clock example, had RDY not been asserted EX destination register), it asserts its enables PCE, ACE, and so forth. The during t4, the pipeline would have FWD output signal, and the A register pipeline registers do not clock, and stalled another cycle to wait for EXL receives the I1 result just in time for this extends all pipeline stages by one access to complete. EX2 in t4. cycle. In Table 2, memory is not ready Unlike most pipelined CPUs, the during the fetch of instruction I3 in t3, BRANCHING OUT xr16 only forwards results to the A and so t4 repeats t3. (Repeated pipe Next, consider the effect of jumps operand—a speed/area tradeoff. The stages are italicized.) (call and jal) and taken branches. assembler handles any rare port B data IL in Listing 1 is a load word in- By the time you execute the jump or struction. Loads and stores need a taken branch IJ during EXJ (updating t1 t2 t3 t4 t5 second memory access, causing pipe- PC), you’ll have decoded IJ+1 and line havoc (see Table 3). In t4 you fetched IJ+2. These instructions in the IF1 DC1 EX1 EX1 must run a load data access instead branch shadow (and their side effects) IF2 DC2 DC2 EX2 IF3 IF3 DC3 of an instruction fetch. You must must be annulled. IF4 stall the pipeline to squeeze in this Continuing the Table 3 example access. from time t5, and assuming the branch Table 2—During t3, the instruction fetch memory access Then, although you fetched I3 in t3, is taken at t7, you must annul the EX5 of I3 is not RDY, so the pipeline registers do not clock, and the pipeline stalls until RDY is asserted in t4. you must not latch it into the stage of I5, and the DC6 and EX6 stages Repeated pipeline stages are italicized. instruction register (IR) as t3 ends, of I6. (Annulled stages are struck 2 Issue 117 April 2000 CIRCUIT CELLAR®
  3. INTERRUPTS Secondly, the int must not be t1 t2 t3 t4 t5 t6 t7 t8 t9 When an interrupt request inserted in a branch or jump shadow, IFL DCL EXL EXL occurs, you must jump to the lest it be annulled. If a branch or jump IF2 DC2 DC2 EX2 interrupt handler, preserve the is in the DC stage, or if a taken IF3 IF3 DC3 EX3 interrupt return address, retire branch or jump is in the EX stage, the IFB DCB EXB the current pipeline, execute interrupt is deferred. IF5 DC5 EX5 IF6 DC6 EX6 the handler, and later return to The simplicity of the process pays IFT DCT the interrupted instruction. off once again. The time to take an When INTREQ is asserted, interrupt and then return from a null Table 3—Pipelined execution of the load instruction IL, I2, I3, the you simply override the interrupt handler is only six cycles. branch IB, the annulled I5 and I6, and the branch target IT. During fetched instruction with int, You might be wondering about the t4 you stall the pipeline for the IL load/store memory cycle. The branch IB executed in t7 causes I5 and I6 to be annulled in t8 and that is, jal r14,10(r0) via interrupt priorities, non-maskable t9. Annulled instructions are struck through. the IRMUX. This jumps to the interrupts, nested interrupts, and interrupt handler at 0x0010 interrupt vectors. These artifacts of through). Execution continues at in- and leaves the return address in r14, the fixed-pinout era need not be struction IT. T9 is not an EX5 load which is reserved for this purpose. hardwired into our FPGA CPU. They cycle, because the I5 load is annulled. When the handler has completed, it are best done by collaboration with an Because you always annul the two executes iret, (i.e, jal r0,0(r14)) on-chip interrupt controller and the branch shadow instructions, jumps and exection resumes with the interrupt handler software. and taken branches take three cycles. interrupted instruction. The last pipeline issue is DMA. Jumps also save the return address in There are two pipeline issues here. The PC/address unit doubles as a the destination register. This return First, you must not interrupt an DMA engine. Using a 16 × 16 RAM as address is obtained from the data- interlocked instruction sequence (any a PC register file, you can fetch either path’s RET register, which holds the add, sub, shift, or imm followed by an instruction (AN ← PC0 += 2) or a address of the instruction in the DC another instruction). If an interlocked DMA word (AN ← PC1 += 2) per pipeline stage. instruction is in the DC stage, the memory cycle. interrupt is deferred one cycle. After an instruction is fetched, if a) b) Mem cycle state machine IF LSP FSM outputs IF DMAP DMAP LSP RDY ACE IF FDPE DMA LSN IF BUF FDCE DMAN PRE RDY DMA IFN D Q DMAN PCE LSP D Q IFN DMAP LSP RDY CE RDY CE CLK C ^ CLK C RDY ^ IF CLR IFN PCCE DMA LS DMAN OR2 EXLDST LSP EXANNUL RDY Annul state machine IFN RETCE DCANNUL EXAN DCINT FDPE RESET EXANNUL RESET FDPE DCAN PRE BRANCH D LSN DCANNUL PRE WORDN Q D Q EXANNUL EXLBSB JUMP PCE CE BRANCH PCE CE CLK C ^ JUMP CLK C ^ INIT=S INIT=S LSN Pending requests EXST READN DMAP ZEROP FJKC FJKC DMAREQ J ZERODMA J K Q DMAP K ZEROP DMA DMA Q LSN DBUSN ZERO BUF CLK C CLK C DMAN ^ ^ CLR CLR DMAN DMAPC BUF INTP IFINT FJKC IREQ J INTP DCINT IFN Q FDCE SELPC IFINT K BRANCH JUMP DMAN PCE D Q DCINT CLK C ^ JUMP PCE CE Zero CLR DCINTINH CLK Reset ZEROPC C CLR RESET FDPE PRE Figure 1—This control unit finite state machine schematic implements GND D Q RESET the symbol CTRLFSM in Figure 2. It consists of the memory cycle FSM RDY CE C (see Figure 4), plus instruction annulment and pending request registers. ^ CLK INIT= S The FSM outputs are derived from the machines current and next states. CIRCUIT CELLAR® Issue 117 April 2000 3
  4. of nanoseconds from the system’s fix are DC stage signals): RNA When critical path. It’s a nice example of a • Nsig: not signal—signal inverted RA DC: add sub addi problem-specific optimization you • DCsig: a DC stage signal lw lb sw sb jal can build with a customizable • EXsig: an EX stage signal RD DC: all rr, ri format processor. • sigN: signal in “next cycle”—input 0 DC: call To recap, each instruction takes to a flip-flop whose output is sig EXRD EX: all but call 15 EX: call three pipeline cycles to move through • sigCE: flip-flop clock enable the instruction fetch, operand fetch • sigT: active low 3-state buffer and decode, and execute pipeline output enable RNB When stages. Each pipeline cycle requires up RB DC: add sub, all rr fmt to three memory access cycles Each instruction flows through the RD DC: sw sb (mandatory instruction fetch, optional three stages (IF, DC, and EX) of the EXRD EX: all but call DMA, and optional EX stage load or control unit (see Figure 2) pipeline. In 15 EX: call store). Each memory access cycle the IF stage, when the instruction requires one or more clock cycles. fetch read completes, the new instruc- Table 4—RNA and RNB control the A and B ports of tion at INSN15:0 is latched into IR. the register file. While CLK is high, they select which registers to read, based upon register fields of the CONTROL UNIT DESIGN In the DC stage, DECODE decodes instruction in the DC stage. While CLK is low, they Now that you understand the pipe- IR to derive internal control signals. select which register to write, based upon the instruc- line, you are ready to design the con- In the first half clock cycle, CTRL tion in the EX stage. trol unit. (For more information on drives RNA3:0 and RNB3:0 with the RISC pipelines, see Computer Orga- source registers to read, and drives DMAREQ has been asserted, you nization and Design: The Hardware/ FWD and IMM5:0 to select the A and B insert one DMA memory cycle. Software Interface, by Patterson and operands. If the instruction is a This PC register file costs eight Hennessy.) [1] First, some important branch, CTRL determines if it is CLBs for the RAM, but saves 16 CLBs naming conventions. Some control taken. Then as the pipeline advances, (otherwise necessary for a separate 16- unit signal names have prefixes and the instruction passes into EXIR. bit DMA address counter and a 16-bit suffixes to recognize their function or In the EX stage, CTRL drives ALU 2-1 address mux), and shaves a couple context (most signal names sans pre- and result mux controls. If the in- INSN[15:0] Instruction registers NEXTIR IR EXIR FD16CE IRMUX FD16CE FD16CE EXIRB EXOP[3:0],EXRD[3:0],BRDISP[7:0] NIR[15:0] IRMUX[15:0] IR[15:0] EXIR[15:0] D[15:0] Q[15:0] A[15:0] O[15:0] D[15:0] Q[15:0] D[15:0] Q[15:0] I[15:0] O[15:0] IF CE B[15:0] PCE CE PCE BRDISP[7:0] IF CE CLK SEL BUF16 C CLK C CLR ^ ^ CLR CLK C CLR ^ IFINT INT IRMUX IRB Control state machine Instruction decoder OP[3:0],RD[3:0],RA[3:0],RB[3:0] DECODE I[15:0] O[15:0] FSM IREQ IREQ PCE PCE OP[3:0] OP[3:0] RRRI RRRI BUF16 DCINTINH DCINTINH ACE ACE IR[7:4] FN[3:0] IMM12 IMM_12 WORDN WORDN IMM4 IMM_4 IMMB READN READN SEXTIMM4 SEXTIMM4 I[15:0] O[15:0] IMM[11:0] EXLDST EXLDST DBUSN DBUSN WORDIMM4 WORDIMM4 IR[11:0] EXLBSB EXLBSB IF IF ADDSUB ADDSUB BUF16 EXST EXST IFINT IFINT SUB SUB BRANCH BRANCH DMA DMA ST ST JUMP JUMP EXAN EXAN CALL CALL EXANNUL EXANNUL NSUM NSUM SELPC SELPC NLOGIC NLOGIC ZERODMA ZERODMA ZEROPC ZEROPC NLW NLW DMAREQ DMAREQ DMAPC DMAPC NLD NLD RDY RDY PCCE PCCE NLB NLB CLK NSR NSR ^ CLK RETCE RETCE NSL NSL CTRLFSM NJAL NJAL BR BR ADCSBC ADCSBC NSUB NSUB DCINTINH DCINTINH Figure 2—This control unit schematic implements EXOP[3:0] EXOP[3:0] EXNSUB EXNSUB half of the symbol CTRL16 in last month’s Figure 2, EXFNSRA EXFNSRA EXIMM including the CPU finite state machine, instruction EXIMM EXLDST EXLDST register pipline, and instruction decoder. Instructions EXLBSB EXLBSB enter on INSN15:0 and are latched in IR and decoded. EXRESULTS EXRESULTS EXJALI EXCALL PCE PCE EXJAL EXJAL CLK CLK ^ 4 Issue 117 April 2000 CIRCUIT CELLAR®
  5. struction is a load/store, it in- 0xAE01 Enable Instruction Source serts a memory access. In the last half cycle, RNA and RNB both SUMT add sub addi SUM15:0 If a DMA or load/store access drive the destination register adc sbc adci sbci is pending, IF enables NEXTIR to number to store the result into LOGICT and or xor andn LOGIC15:0 capture the previously fetched andi ori xori andni the register file. instruction (take a look back at SLT slli A14:0 || 0 Let’s consider each part of the SRT srli srai SRI || A15:1 time t3 in Table 3). Otherwise, control finite state machine (see ZXT lb 015:8 the instruction fetch is the only Figure 1). The control FSM has RETADT jal call RETAD15:0 memory access in the pipe stage. none sw sb br* imm — three states: So, IF is then asserted with PCE, and IRMUX selects the INSN15:0 Table 5—Here’s a look at the result multiplexer output enable controls. • IF: current memory access is an The instruction determines which enable is asserted and which function input as the next instruction to instruction fetch cycle unit drives RESULT15:0. complete. • DMA: current access is a DMA cycle • RDY: memory cycle complete (input DECODE STAGE • LS: current access is a load/store from the memory controller) The greater part of the control unit • READN: next memory cycle is a operates in the DC stage. It must Figure 4 shows the state transition read transaction—true except for decode the new instruction, control diagram. The FSM clocks when one stores the register file, the A and B operand memory transaction completes and • WORDN: next cycle is 16-bit data— multiplexers, and prepare most EX another begins (on RDY). CTRLFSM true except for byte loads/stores stage control signals. also has several other bits of state: • DBUSN: next cycle is a load/store, The instruction register IR latches and it needs the on-chip data bus the new instruction word as the DC • DCANNUL: annul DC stage • ACE (address clock enable): the next stage begins. The buffers IRB and • EXANNUL: annul EX stage address AN15:0 (a datapath output) IMMB break out the instruction fields • DCINT: int in DC stage and the above control outputs are OP, RD, and so forth—IR15:12 is re- • DMAP: DMA transfer pending all valid, so start a new memory named OP3:0 and so on (the tools opti- • INTP: interrupt pending transaction in the next clock cycle. mize away these buffers). ACE equals RDY, because if The instruction decoder DECODE DCANNUL and EXANNUL are set memory is ready, the CPU is is simple. It is a set of 30 ROM 16x1s, after executing a jump or taken always eager to start another gate expressions, and a handful of flip- branch. They suppress any effects of memory transaction. flops. Each ROM inputs OP3:0 or the two instructions in the branch There are no IF stage control out- EXOP3:0 and outputs some decoded shadow, including register file write- puts. Internal to the control unit, signal. The decoder is relatively back and load/store memory accesses. three signals control IF stage re- compact because xr16 has a simple So, an annulled add still fetches and sources. Those three signals are: instruction set, and its 4-bit opcodes adds its operands, but its results are are a good match for the FPGA’s 4 not retired to the register file. • PCE: enable IR and EXIR LUTs. DCINT is set in the pipeline cycle clocking The register file control signals, following the insertion of the int • IF: asserted in an instruction shared by both the DC and EX stages, instruction. It inhibits clocking of fetch memory cycle are RNA3:0: port A register number; RET for one cycle, so that the int • IFINT: force the next instruction to RNB3:0: port B register number; and picks up the return address of the be int = jal r14,10(r0) = RFWE: register file write enable. interrupted instruction rather than the instruction after that. The highest fan-out control signal is Next cycle Next address Outputs PCE, the pipeline clock enable. Most datapath registers are enabled by PCE. IF AN ← PC0 += 2 SELPC PCCE IF branch AN ← PC0 += 2×disp8 BRANCH SELPC PCCE It indicates that all pipe stages are ready and the pipeline can advance. IF jal call AN ← PC0 = SUM PCCE PCE is asserted when RDY signals completion of the last memory cycle IFreset AN ← PC0 = 0 SELPC ZEROPC PCCE in the current pipeline cycle. If mem- LS load/store AN ← SUM — ory isn’t ready, PCE isn’t asserted, and the pipeline stalls for one cycle. DMA AN ← PC1 += 2 SELPC DMAPC PCCE The control FSM also takes care of DMA reset AN ← PC1 = 0 SELPC ZEROPC DMAPC PCCE managing the memory interface via Table 6—Here’s a look at the result multiplexer output enable controls. The instruction determines which enable to the following signals: assert and thus determines which function unit drives the RESULT bus. CIRCUIT CELLAR® Issue 117 April 2000 5
  6. With CLK high, by adding 2×disp8 to DC: operand selection CTRL drives RNA EXRESULTS Execute stag e the PC. PCE CI and RNB with the EXANNUL RFWE NSUB FDCE DC stage RZERO ADCSBC CO D Q CE CI THE EXECUTE PCE instruction’s source RNA CLK C STAGE ^ RA[3:0] RA[3:0] RN[3:0] RNA[3:0] register numbers. RD[3:0] RD[3:0] FWD CLR Now, let’s discuss With CLK low, RRRI SELRD EXRESULTS FWD the EX stage ALU, CALL SELR0 EXANNUL CTRL drives RNA EXRD[3:0] EXRD[3:0] RZERO RZERO AND3B1 result mux, and EXCALL SELR15 EXNSUB ADD and RNB with the CLK SELSRC BUF address unit controls. EX stage destination RNMUX4 LOGICOP[1:0] The ALU and shift RLOC=R2C0 register number. EXIR4 BUF LOGICOP0 control outputs are: RNB EXIR5 LOGICOP1 RFWE is asserted RB[3:0] RA[3:0] RN[3:0] RNB[3:0] BUF with PCE when RD[3:0] RD[3:0] FWD "N.C." EXFNSRA SRI • ADD: set unless the ST SELRD SRI there is a result to GND SELR0 A15 instruction is sub or write back. It is false EXRD[3:0] EXCALL EXRD[3:0] RZERO "N.C." SELR15 sbc for instructions, CLK SELSRC T1 • CI: carry-in. 0 for which produces no RNMUX4 RLOC=R2C1 NSUM D0 Q0 NLOGIC D1 Q1 SUMT LOGICT add and 1 for sub, result (immediate NLW D2 Q2 "N.C." unless it’s adc or sbc NLD D3 Q3 "N.C." prefix, branch, or PCE CE where we XOR in the IR3 IMMOP[5:0] CLK store) for annulled CLK previous carry-out ^ SEXTIMM4 IMMOP0 IMM_12 FD4PE instructions, and for INIT= S • LOGICOP1:0: select destination r0. WORDIMM4 IR0 IMMOP1 T2 and, or, xor, or andn. NLB D0 Q0 ZXT The muxes RNA NSR D1 Q1 SRT LOGICOP1:0 is simply IMM_4 IMMOP2 and RNB produce IMM_4 BUF IMMOP3 NSL D2 Q2 SLT EXIR5:4 (i.e., EX stage BUF NJAL D3 Q3 RETARDT RNA3:0 and RNB3:0, as IMM_12 IMMOP4 PCE CE copy of FN1:0) BUF ^ CLK CLK shown in Table 4, as WORDMM4 IR0 IMMOP5 • SRI: shift right FD4PE selected by decode EXIMM PCE INIT= S input—0 for srli and BCE15_4 outputs RRRI, EXANNUL EXJAL JUMP A15 for srai (shift EXANNUL CALL, ST, EXCALL, DC:conditional branches right arithmetic) BRANCH and CLK. Call is TRUE TRUE FDCE Z Z TRUE BRN irregular. It N N BR D Q DMAPC BRANCH slxi and srxi (shift EXAN PCE CE computes r15 = pc, CO C extended left/right for V V CLK C pc = r0 + imm12
  7. SP ×L *DMA P *LSP DMA IF DMA P LSP *D M P A ×L SP LS DMAP: DMA pending LSP: load/store pending Figure 4—Each memory cycle is an instruction fetch unless there is a DMA transfer pending or the EX stage instruction is a load or store. The FSM clocks when one memory transaction completes and another begins (on RDY). • DMAPC: if set, fetch and update PC1 (DMA address), otherwise PC0 (PC) Depending on the next memory cycle and the current EX stage instruction, the control unit selects the next address by asserting certain combinations of control outputs (see Table 6). WRAP-UP This month, we considered pipe- lined processor design issues and ex- plored the detailed implementation of our xr16 control unit—and lived! The CPU design a software developer Jan Gray is is complete. The final whose products include a leading C++ article in this series tackles the design of this System-on-a-Chip. I compiler. He has been building FPGA processors and systems since 1994, and he now designs for Gray Re- search LLC. You may reach him at SOFTWARE Visit the Circuit Cellar web site for more information, including specifications, source code, schematics, and links to related sites. REFERENCE [1] D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann, San © Circuit Cellar, The Magazine for Computer Applications. Mateo, CA, 1994. Reprinted with permission. For subscription information call (860) 875-2199, email or on our web site at CIRCUIT CELLAR® Issue 117 April 2000 7
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