Chapter8: State Machine

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Output o is declared a reg because it is assigned procedurally, not because it holds state. Combinational block must be sensitive to any change on any of its inputs...

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Nội dung Text: Chapter8: State Machine

NATIONAL UNIVERSITY OF HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING LECTURE VERILOG Subject: Hardware Design Language Chapter8: State Machine Lecturer: Lam Duc Khai 1
Agenda 1. Chapter 1: Introduction ( Week1) 2. Chapter 2: Fundamental concepts (Week1) 3. Chapter 3: Modules and hierarchical structure (Week2) 4. Chapter 4: Primitive Gates – Switches – User defined primitives (Week2) 5. Chapter 5: Structural model (Week3) 6. Chapter 6: Behavioral model – Combination circuit & Sequential circuit (Week4 & Week5) 7. Chapter 7: Tasks and Functions (Week6) 8. Chapter 8: State machines (Week6) 9. Chaper 9: Testbench and verification (Week7) 2
Why FSM ? 3
Finite State Machine • Moore FSM model inputs comb. next memory current comb. outputs state state circuit elements circuit Next state = F (current state, inputs) Outputs = G (current state) 4
Finite State Machine • Moore FSM model 5
Finite State Machine • Mealy FSM model next current inputs comb. state memory state comb. outputs circuit elements circuit Next state = F (current state, inputs) Outputs = G (current state, inputs) 6
Finite State Machine • Mealy FSM model 7
FSMs modeling • There are many ways to model FSMs: Method1: Define the next-state logic combinationally and define the state-holding latches explicitly Method2: Define the behavior in a single always @(posedge clk) block • Variations on these themes 8
FSMs modeling Method1: Output o is declared a reg because it is assigned module FSM(o, a, b, reset); procedurally, not because it output o; holds state reg o; Combinational block must be input a, b, reset; sensitive to any change on reg [1:0] state, nextState; any of its inputs (Implies state-holding always @(a or b or state) elements otherwise) case (state) 2’b00: begin Latch implied by sensitivity nextState = a ? 2’b00 : 2’b01; to the clock or reset only o = a & b; end always @(posedge clk or reset) 2’b01: begin nextState = 2’b10; if (reset) o = 0; state
FSMs modeling Method2: module FSM(o, a, b); output o; reg o; input a, b; reg [1:0] state; always @(posedge clk or reset) if (reset) state
Example1: A Moore 101 Detector 11
Example1: A Moore 101 Detector ( Cont’d) module Moore101Detector (dataIn, found, clock, reset); //Input and Output Declarations input dataIn; input clock; input reset; output found; //DataInternal Variables reg [3:0] state; reg [3:0] next_state; //State Declarations parameter reset = 3'b000; parameter got1 = 3'b001; parameter got10 = 3'b010; parameter got101 = 3'b101; 12
Example1: A Moore 101 Detector ( Cont’d) got101: //Combinational Next State Logic if (dataIn) always @(state or dataIn) next_state = got1; case (state) else reset: next_state = got10; if (dataIn) default: next_state = got1; next_state = reset; else endcase // case(state) next_state = reset; got1: //State FF Transition if (dataIn) always @(posedge clock) next_state = got1; if (reset == 1) else state
Example2: A Mealy 101 Detector 14
Example2: A Mealy 101 Detector (Cont’d) module Mealy101Detector (dataIn, found, clock, reset); //Input and Output Declarations input dataIn; input clock; input reset; output found; //DataInternal Variables reg [3:0] state; reg [3:0] next_state; //State Declarations parameter reset = 3'b000; parameter got1 = 3'b001; parameter got10 = 3'b010; 15
Example2: A Mealy 101 Detector (Cont’d) default: //Combinational Next State Logic next_state = reset; always @(state or dataIn) endcase // case(state) case (state) reset: //State FF Transition if (dataIn) always @(posedge clock) next_state = got1; if (reset == 1) else state
Example3: Traffic Light Controller Picture of Highway/Farmroad Intersection: Farmroad C HL FL Highway Highway FL HL C Farmroad 17
Example3: Traffic Light Controller (Cont’d) Specifications ? Tabulation of Inputs and Outputs: Input Signal Description reset place FSM in initial state C detect vehicle on farmroad TS short time interval expired TL long time interval expired Output Signal Description HG, HY, HR assert green/yellow/red highway lights FG, FY, FR assert green/yellow/red farmroad lights ST start timing a short or long interval ? Tabulation of Unique States: Some light configuration imply others Description State Highway green (farmroad red) S0 Highway yellow (farmroad red) S1 Farmroad green (highway red) S2 Farmroad yellow (highway red) S3 18
Example3: Traffic Light Controller (Cont’d) Block diagram HR C n_state state HG Comb. Comb. FF’s HY TS circuits circuits FR TL FG FY 19
Example3: Traffic Light Controller (Cont’d) State transition diagram TL + C S0: HG Reset S1: HY S0 TL•C/ST TS/ST S2: FG TS S3: FY S1 S3 TS TS/ST TL + C/ST S2 TL • C 20