Network signal processing

Bài giảng HDL & FPGA - Chương 5: Các vấn đề khác. Chương này cung cấp cho sinh viên những nội dung kiến thức gồm: interesting topics in the field of Reconfigurable Computing (FPGA); Network-on-Chip - bối cảnh ra đời; Signal processing & Machine learning applications on FPGA; Hybrid reconfigurable CPUs; một vài ứng dụng trên FPGA;... Mời các bạn cùng tham khảo!

17p nguyetthuongvophong1010 04-03-2024 5 1   Download

Đề tài "Nhận dạng vết nứt của bánh răng bằng phương pháp đo dao động và phép biến đổi Wavelet rời rạc" trình bày ứng dụng của việc phân tích số tín hiệu dao động cơ học và mạng neural để phát hiện hƣ hỏng, vết nứt bánh răng trong hộp số. Phép phân tích tín hiệu đƣợc sử dụng là phép biến đổi Wavelet rời rạc, mạng nơron đƣợc sử dụng là mạng nơron truyền thẳng đa lớp MLP, chƣơng trình tính toán đƣợc thực hiện trên phần mềm Matlab với công cụ Signal Processing Toolbox, Neural Networks Toolbox.

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Metabolically unstable proteins are involved in a multitude of regulatory networks, including those that control cell signaling, the cell cycle and in many responses to physiological stress. In the present study, we have deter-mined the stability and characterized the degradation process of some members of the Gq class of heterotrimeric G proteins. Pulse-chase experi-ments in HEK293 cells indicated a rapid turnover of endogenously expressed Gaq and overexpressed Gaq and Ga16 subunits.

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Nephrin is a signalling cell–cell adhesion protein of the Ig superfamily and the first identified component of the slit diaphragm that forms the critical and ultimate part of the glomerular ultrafiltration barrier. The extracellular domains of the nephrin molecules form a network of homophilic and heterophilic interactions building the structural scaffold of the slit dia-phragm between the podocyte foot processes.

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EURASIP Journal on Applied Signal Processing 2003:10, 1016–1026 c 2003 Hindawi Publishing Corporation Model-Based Speech Signal Coding Using Optimized Temporal Decomposition for Storage and Broadcasting Applications Chandranath R. N. Athaudage ARC Special Research Center for Ultra-Broadband Information Networks (CUBIN), Department of Electrical and Electronic Engineering, The University of Melbourne, Victoria 3010, Australia Email: cath@ee.mu.oz.au Alan B. Bradley Institution of Engineers Australia, North Melbourne, Victoria 3051, Australia Email: abradley@ieaust.org.

11p sting12 10-03-2012 44 6   Download

EURASIP Journal on Applied Signal Processing 2003:4, 378–391 c 2003 Hindawi Publishing Corporation Collaborative In-Network Processing for Target Tracking Juan Liu Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA Email: jjliu@parc.com James Reich Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA Email: jreich@parc.com Feng Zhao Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA Email: zhao@parc.

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EURASIP Journal on Applied Signal Processing 2003:7, 620–628 c 2003 Hindawi Publishing Corporation Analog VLSI Circuits for Short-Term Dynamic Synapses Shih-Chii Liu Institute of Neuroinformatics, University of Zurich and ETH Zurich, Winterthurerstrasse 190, CH-8057 Zurich, Switzerland Email: shih@ini.phys.ethz.ch Received 14 May 2002 and in revised form 25 September 2002 Short-term dynamical synapses increase the computational power of neuronal networks. These synapses act as additional filters to the inputs of a neuron before the subsequent integration of these signals at its cell body.

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EURASIP Journal on Applied Signal Processing 2003:12, 1229–1237 c 2003 Hindawi Publishing Corporation Nonlinear System Identification Using Neural Networks Trained with Natural Gradient Descent Mohamed Ibnkahla Electrical and Computer Engineering Department, Queen’s University, Kingston, Ontario, Canada K7L 3N6 Email: mohamed.ibnkahla@ece.queensu.ca Received 13 December 2002 and in revised form 17 May 2003 We use natural gradient (NG) learning neural networks (NNs) for modeling and identifying nonlinear systems with memory.

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EURASIP Journal on Applied Signal Processing 2003:9, 890–901 c 2003 Hindawi Publishing Corporation An Efficient Feature Extraction Method with Pseudo-Zernike Moment in RBF Neural Network-Based Human Face Recognition System Javad Haddadnia Engineering Department, Tarbiat Moallem University of Sabzevar, Sabzevar, Khorasan 397, Iran Email: haddadnia@sttu.ac.ir Majid Ahmadi Electrical and Computer Engineering Department, University of Windsor, Windsor, Ontario, Canada N9B 3P4 Email: ahmadi@uwindsor.

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EURASIP Journal on Applied Signal Processing 2003:3, 276–286 c 2003 Hindawi Publishing Corporation Robust Clustering of Acoustic Emission Signals Using Neural Networks and Signal Subspace Projections Vahid Emamian Department of Electrical & Computer Engineering, University of Minnesota, 200 Union St. SE, Minneapolis, MN 55455, USA Email: emamian@ieee.org Mostafa Kaveh Department of Electrical & Computer Engineering, University of Minnesota, 200 Union St. SE, Minneapolis, MN 55455, USA Email: mos@ece.umn.edu Ahmed H.

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Hindawi Publishing Corporation EURASIP Journal on Advances in Signal Processing Volume 2008, Article ID 529879, 16 pages doi:10.1155/2008/529879 Research Article Biometric Methods for Secure Communications in Body Sensor Networks: Resource-Efficient Key Management and Signal-Level Data Scrambling Francis Minhthang Bui and Dimitrios Hatzinakos The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King’s College Road, Toronto, Ontario, Canada M5S 3G4 Correspondence should be addressed to Dimitrios Hatzinakos, dimitris@comm.utoronto.

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Hindawi Publishing Corporation EURASIP Journal on Advances in Signal Processing Volume 2008, Article ID 479357, 17 pages doi:10.1155/2008/479357 Research Article Uplink SDMA with Limited Feedback: Throughput Scaling Kaibin Huang, Robert W. Heath Jr., and Jeffrey G. Andrews Wireless Networking and Communications Group, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712-0240, USA Correspondence should be addressed to Kaibin Huang, huangkb@mail.utexas.edu Received 15 June 2007; Accepted 23 October 2007 Recommended by Christoph F.

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Hindawi Publishing Corporation EURASIP Journal on Advances in Signal Processing Volume 2008, Article ID 468693, 7 pages doi:10.1155/2008/468693 Research Article Comparing Robustness of Pairwise and Multiclass Neural-Network Systems for Face Recognition J. Uglov, L. Jakaite, V. Schetinin, and C. Maple Computing and Information System Department, University of Bedfordshire, Luton LU1 3JU, UK Correspondence should be addressed to V. Schetinin, vitaly.schetinin@beds.ac.uk Received 16 June 2007; Revised 28 August 2007; Accepted 19 November 2007 Recommended by Konstantinos N.

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Hindawi Publishing Corporation EURASIP Journal on Advances in Signal Processing Volume 2008, Article ID 286168, 10 pages doi:10.1155/2008/286168 Research Article Extension of Pairwise Broadcast Clock Synchronization for Multicluster Sensor Networks Kyoung-Lae Noh,1 Yik-Chung Wu,2 Khalid Qaraqe,3 and Bruce W. Suter4 1 Digital Solution Center, Corporate Technology Operations, Samsung Electronics Co., Ltd., South Korea of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong 3 Texas A&M University at Qatar, P.O.

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Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article Detecting Network Intrusions Using Signal Processing with Query-Based Sampling Filter

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Digital output modules can be used to output digital signals from the control to the process. They convert the internal signal levels of the S7-300 into the external signal levels required for the process. They are suitable e.g., for connecting solenoid valves, contactors, small-power motors, lamps and motor starters.

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Digital input modules can be used to connect the PLC to digital process signals. They are suitable for connecting standard switches and two-wire proximity switches (BERO).

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The analog output modules convert digital signals from the PLC into analog signals for the process. The modules feature the following: Resolution from 12 to 15 bit Various voltage and current ranges: The ranges are set independently for each channel using parameterization software. Interrupt capability: The module transmits diagnostic alarm messages to the controller’s CPU in the event of errors.

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The analog input modules convert analog signals from the process into digital signals for processing within the PLC. The modules feature: Resolution from 9 to 15 bits + sign (for different conversion times), configurable Different measuring ranges; the basic current/voltage range settings are adjusted mechanically via measurement range modules. Fine adjustments are made with the STEP 7 Hardware Configuration tool on a PG.

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