Processor

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  • Word processors or computers used in Japan employ Japanese input method through keyboard stroke combined with Kana (phonetic) character to Kanji (ideographic, Chinese) character conversion technology. The key factor of Kana-to-Kanji conversion technology is how to raise the accuracy of the conversion through the homophone processing, since we have so many homophonic Kanjis. In this paper, we report the results of our Kana-to-Kanji conversion experiments which embody the homophone processing based on large scale collocation data. ...

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  • Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as runahead and out-of-order execution that require non-blocking caches to tolerate main memory latencies. Conventional nonblocking caches are expensive and slow on FPGAs as they use content-addressable memories (CAMs). This work exploits key properties of runahead execution and demonstrates an FPGA-friendly non-blocking cache design that does not require CAMs.

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  • This paper presents a practical foreign language writing support tool which makes it much easier to utilize dictionary and example sentence resources. Like a Kana-Kanji conversion front-end processor used to input Japanese language text, this tool is also implemented as a front-end processor and can be combined with a wide variety of applications. A morphological analyzer automatically extracts key words from text as it is being input into the tool, and these words are used to locate information relevant to the input text. ...

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  • A language processor is to find out a most promising sentence hypothesis for a given word lattice obtained from acoustic signal recognition. In this paper a new language processor is proposed, in which unification granunar and Markov language model are integrated in a word lattice parsing algorithm based on an augmented chart, and the island-driven parsing concept is combined with various preference-first parsing strategies defined by different construction principles and decision rules.

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  • The Layered Domain Class system (LDC) is an experimental natural language processor being developed at Duke University which reached the prototype stage in M a y of 1983. Its primary goals are (I) to provide English-language retrieval capabilities for structured but unnormaUzed data files created by the user, (2) to allow very complex semantics, in terms of the information directly available from the physical data file; and (3) to enable users to customize the system to operate with new types of data. In this paper we shall discuss (a) the types of modifiers LDC provides for; (b) h o...

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  • A new approach to bottom-up parsing that extends Augmented Context-Free Grammar to a Process Grammar is formally presented. A Process Grammar (PG) defines a set of rules suitedfor bottom-up parsing and conceived as processes that are applied by a P G Processor. The matching phase is a crucial step for process application, and a parsing structure for efficient matching is also presented. The PG Processor is composed of a process scheduler that allows immediate constituent analysis of structures, and behaves in a non-deterministic fashion. ...

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  • Operating System: Chapter 8 - Multiple Processor Systems provides about Multiprocessors, Multiprocessor Hardware, Multiprocessor OS Types, Multiprocessor Synchronization, Multiprocessor Scheduling, Multicomputers, Distributed systems.

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  • We discuss ways of allowing the users of a natural language processor to define, examine, and modify the definitions of any domain-specific words or phrases known to the system. An implementation of this work forms a critical portion of the knowledge acquisition component of our Transportable English-Language Interface (TELl), which answers English questions about tabular (first normal-form) data files and runs on a Symbolics Lisp Machine.

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  • Comparative expressions (CEs) such as "bigger than" and "more oranges than" are highly ambiguous, and their meaning is context dependent. Thus, they pose problems for the semantic interpretation algorithms typically used in natural language database interfaces. We focus on the comparison attribute ambiguities that occur with CEs. To resolve these ambiguities our natural language interface interacts with the user, finding out which of the possible interpretations was intended.

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  • In this paper, we present a morphological processor for Modern Greek. From the linguistic point of view, we tr5, to elucidate the complexity of the inflectional system using a lexical model which follows the mecent work by Lieber, 1980, Selkirk 1982, Kiparsky 1982, and others. The implementation is based on the concept of "validation grammars" (Coumtin 1977). The morphological processing is controlled by a finite automaton and it combines a. a dictionary containing the stems for a representative fragment of Modern Greek and all the inflectional affixes with b.

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  • This work proposes a processor architecture for elliptic curves cryptosystems over fields GF (2m ). This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields.

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  • In this paper, we present the design and implementation of a 64-bit reduced instruction set (RISC) processor with built-in-self test (BIST) features.

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  • In this condition, we can use some of processors instead of all of them to help reducing power consumption. As a hypothesis, turning processors with low processing load off can reduce the power consumption in such a way that response time of processes stay acceptable. In this paper, we discuss about a new policy to manage turning processors on/off during run time of system to examine the mentioned hypothesis.

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  • Microcontroller is a computer that is integrated on a chip, it is often used to control electronic devices. Microcontroller, in essence, is a system including a processor with enough performance and low cost (other than multi-purpose microprocessors used in computers) combined with peripheral blocks as the remember, the modular input / output, the module to change the analog and analog to digital, ... In the computer modules are usually built by the chips and circuits.

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  • GPU

    GPU viết tắt của Graphic Processor Unit là đơn vị xử lý tín hiệu đồ họa GPU được hình thành và phát triển tử rất sớm và có lịch sử lâu đời tương tự như CPU GPU được phân thành nhiều nhóm có nhiều chức năng khác nhau giúp người dùng dễ dàng lựa chọn theo nhu cầu dữ dụng đồ họa

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  • Tham khảo bài thuyết trình 'kiến trúc máy tính: bộ xử lý - processor', công nghệ thông tin, phần cứng phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả

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  • Modern electronic systems are increasingly digital: digital microprocessors, digital logic, digital interfaces. Digital logic is easier to design and understand, and it is much more flexible than the equivalent analog circuitry would be. As an example, imagine trying to implement any kind of sophisticated micro- processor with analog parts. Digital electronics lets the PC on your desk execute different programs at different times, perform complex calculations, and communicate via the World Wide Web....

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  • Mục lục - Chương I: Nhứng khái niệm cơ bản; Chương II: Quản lý thiết bị; Chương III: Quản lỹ bộ nhớ; Chương IV: Qủan lỹ tiến trình; Chương V: Hệ điều hành Processor

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  • Introduction Nowadays, the communication possibilities between automation systems are a core demand and necessity, even in the case of systems of the lower performance class. Due to the large variety of communication processors, protocols and user interfaces in the SIMATIC homogenous system world (i.e. only SIMATIC systems communicate with each other) and particularly in the heterogeneous system world (i.e. SIMATIC systems communicate with “third party” automation systems) this topic is extremely complex.

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  • Bài giảng "Nguyên lí hệ điều hành" trình bày nội dung thông qua các chương sau: chương 1 những khái niệm cơ bản, chương 2 quản lý tiến trình, chương 3 quản lý bộ nhớ, chương 4 quản lý thiết bị, chương 5 hệ điều hành nhiều Processor.

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