The parallel Implementation

Parallel Implementation of MAFFT on CUDA-Enabled Graphics Hardware present a new approach to accelerat- ing MAFFT on Graphics Processing Units (GPUs) using the Compute Unified Device Architecture (CUDA) programming model. Compared with the implementations of other MSA algorithms on GPUs, parallelization of MAFFT is more challenging since the space complexity.

14p ducla78 30-07-2015 48 6   Download

Special issue paper PAR-3D-BLAST: A parallel tool for searching and aligning protein structures present a parallel tool, parallel 3D-BLAST (PAR-  3D-BLAST), which lists the similar structures to the query protein. Each protein in the result list has a  structural similarity score and an alignment to the query structure. The presented tool is implemented to fit  both the standalone multi-core computers and clusters of multi-core nodes. The achieved speedup is linear  and scalable.

10p ducla78 30-07-2015 39 3   Download

Geo-electrical tomographical software plays a crucial role in geophysical research. However, imported software is expensive and does not provide much customizability, which is essential for more advanced geophysical study. Besides, these programs are unable to exploit the full potential of modern hardware, so the running time is inadequate for large-scale geophysical surveys. It is therefore an essential task to develop domestic software for overcoming all these problems.

60p 01202750693 09-06-2015 62 13   Download

We describe Joshua (Li et al., 2009a)1 , an open source toolkit for statistical machine translation. Joshua implements all of the algorithms required for translation via synchronous context free grammars (SCFGs): chart-parsing, n-gram language model integration, beam- and cubepruning, and k-best extraction. The toolkit also implements suffix-array grammar extraction and minimum error rate training. It uses parallel and distributed computing techniques for scalability.

4p hongphan_1 15-04-2013 46 2   Download

EURASIP Journal on Applied Signal Processing 2003:6, 530–542 c 2003 Hindawi Publishing Corporation An FPGA Implementation of (3, 6)-Regular Low-Density Parity-Check Code Decoder Tong Zhang Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180, USA Email: tzhang@ecse.rpi.edu Keshab K. Parhi Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA Email: parhi@ece.umn.

13p sting12 10-03-2012 45 8   Download