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The Verilog Hardware Description Language

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The Verilog Hardware Description Language

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Các ngôn ngữ Verilog là một ngôn ngữ mô tả phần cứng cung cấp một phương tiện chỉ định một hệ thống kỹ thuật số tại một loạt các mức độ trừu tượng. Ngôn ngữ hỗ trợ các khái niệm giai đoạn đầu của thiết kế với mức độ hành vi của nó trừu tượng, và việc thực hiện giai đoạn sau này với sự trừu tượng hóa cấu trúc của nó. Ngôn ngữ bao gồm phân cấp xây dựng, cho phép các nhà thiết kế để kiểm soát sự phức tạp của một mô tả...

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Nội dung Text: The Verilog Hardware Description Language

  1. The Verilog® Hardware Description Language, Fifth Edition
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  3. The Verilog® Hardware Description Language, Fifth Edition Donald E. Thomas ECE Department Carnegie Mellon University Pittsburgh, PA Philip R. Moorby Co-design Automation, Inc. www.co-design.com Verilog® is a registered trade mark of Cadence Design Systems, Inc.
  4. eBook ISBN: 0-306-47666-5 Print ISBN: 1-4020-7089-6 ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2002 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: http://kluweronline.com and Kluwer's eBookstore at: http://ebooks.kluweronline.com
  5. To Sandie, and John and Holland, and Jill.
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  7. Preface xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 7 Creating Ports For the Module Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits 12 Procedural Models Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits 15 Modeling Finite State Machines 18 Rules for Synthesizing Sequential Systems 19 Non-Blocking Assignment ("
  8. The Verilog Hardware Description Language viii Complications — Inferred Latches 42 Using Case Statements 43 Specifying Don' t Care Situations 44 Procedural Loop Constructs 46 48 Inferring Sequential Elements Latch Inferences 48 50 Flip Flop Inferences Summary 52 Inferring Tri-State Devices 52 Describing Finite State Machines 53 An Example of a Finite State Machine 53 56 An Alternate Approach to FSM Specification Finite State Machine and Datapath 58 58 A Simple Computation A Datapath For Our System 58 Details of the Functional Datapath Modules 60 Wiring the Datapath Together 61 Specifying the FSM 63 Summary on Logic Synthesis 66 68 Exercises 3 Behavioral Modeling 73 Process Model 73 If-Then-Else 75 Where Does The ELSE Belong? 80 The Conditional Operator 81 82 Loops Four Basic Loop Statements 82 Exiting Loops on Exceptional Conditions 85 Multi-way Branching 86 If-Else-If 86 Case 86 Comparison of Case and If-Else-If 89 Casez and Casex 90 Functions and Tasks 91 Tasks 93 Functions 97 A Structural View 100 Rules of Scope and Hierarchical Names 102 Rules of Scope 102 Hierarchical Names 105
  9. ix Summary 106 Exercises 106 4 Concurrent Processes 109 109 Concurrent Processes Events 111 112 Event Control Statement 113 Named Events The Wait Statement 116 117 A Complete Producer-Consumer Handshake Comparison of the Wait and While Statements 120 121 Comparison of Wait and Event Control Statements 122 A Concurrent Process Example 128 A Simple Pipelined Processor 128 The Basic Processor 130 Synchronization Between Pipestages 132 Disabling Named Blocks 134 Intra-Assignment Control and Timing Events 136 Procedural Continuous Assignment 138 Sequential and Parallel Blocks 140 Exercises 5 143 Module Hierarchy 143 Module Instantiation and Port Specifications 146 Parameters 150 Arrays of Instances 151 Generate Blocks 154 Exercises
  10. The Verilog Hardware Description Language x 6 157 Logic Level Modeling Introduction 157 Logic Gates and Nets 158 159 Modeling Using Primitive Logic Gates 162 Four-Level Logic Values 163 Nets 166 A Logic Level Example 171 Continuous Assignment 172 Behavioral Modeling of Combinational Circuits 174 Net and Continuous Assign Declarations 176 A Mixed Behavioral/Structural Example Logic Delay Modeling 180 A Gate Level Modeling Example 181 Gate and Net Delays 182 185 Specifying Time Units Minimum, Typical, and Maximum Delays 186 187 Delay Paths Across a Module Summary of Assignment Statements 189 Summary 190 Exercises 191 7 Cycle-Accurate Specification 195 Cycle-Accurate Behavioral Descriptions 195 Specification Approach 195 A Few Notes 197 Cycle-Accurate Specification 198 Inputs and Outputs of an Always Block 198 Input/Output Relationships of an Always Block 199 Specifying the Reset Function 202 Mealy/Moore Machine Specifications 203 A Complex Control Specification 204 Data and Control Path Trade-offs 204 Introduction to Behavioral Synthesis 209 Summary 210
  11. xi 8 Advanced Timing 211 Verilog Timing Models 211 Basic Model of a Simulator 214 Gate Level Simulation 215 Towards a More General Model 215 Scheduling Behavioral Models 218 Non-Deterministic Behavior of the 220 Simulation Algorithm Near a Black Hole 221 It' s a Concurrent Language 223 226 Non-Blocking Procedural Assignments 226 Contrasting Blocking and Non-Blocking Assignments 227 Prevalent Usage of the Non-Blocking Assignment 228 Extending the Event-Driven Scheduling Algorithm Illustrating Non-Blocking Assignments 231 233 Summary 234 Exercises 9 239 User-Defined Primitives 240 Combinational Primitives 240 Basic Features of User-Defined Primitives 242 Describing Combinational Logic Circuits 243 Sequential Primitives 244 Level-Sensitive Primitives 244 Edge-Sensitive Primitives 246 Shorthand Notation 246 Mixed Level- and Edge-Sensitive Primitives 249 Summary 249 Exercises
  12. The Verilog Hardware Description Language xii 10 Switch Level Modeling 251 251 A Dynamic MOS Shift Register Example 256 Switch Level Modeling 256 Strength Modeling 259 Strength Definitions An Example Using Strengths 260 262 Resistive MOS Gates 263 Ambiguous Strengths 264 Illustrations of Ambiguous Strengths 265 The Underlying Calculations The miniSim Example 270 270 Overview 271 The miniSim Source Simulation Results 280 281 Summary 281 Exercises 11 Projects 283 Modeling Power Dissipation 283 284 Modeling Power Dissipation 284 What to do Steps 285 A Floppy Disk Controller 286 Introduction 286 Disk Format 287 Function Descriptions 288 Reality Sets In… 291 Everything You Always Wanted to Know about CRC's 291 Supporting Verilog Modules 292 Appendix A: Tutorial Questions and Discussion 293 Structural Descriptions 293 Testbench Modules 303 Combinational Circuits Using always 303
  13. xiii Sequential Circuits 305 Hierarchical Descriptions 308 Appendix B: Lexical Conventions 309 White Space and Comments 309 Operators 310 Numbers 310 Strings 311 312 Identifiers, System Names, and Keywords Appendix C: Verilog Operators 315 Table of Operators 315 320 Operator Precedence 321 Operator Truth Tables 322 Expression Bit Lengths 323 Appendix D: Verilog Gate Types 323 Logic Gates 325 BUF and NOT Gates 326 BUFIF and NOTIF Gates 327 MOS Gates 328 Bidirectional Gates 328 CMOS Gates 328 Pullup and Pulldown Gates Appendix E: Registers, Memories, Integers, 329 and Time 329 Registers 330 Memories 331 Integers and Times 333 Appendix F: System Tasks and Functions 333 Display and Write Tasks 334 Continuous Monitoring 335 Strobed Monitoring 335 File Output 336 Simulation Time 336 Stop and Finish 336 Random 337 Reading Data From Disk Files 339 Appendix G: Formal Syntax Definition 339 Tutorial Guide to Formal Syntax Specification
  14. The Verilog Hardware Description Language xiv 343 Source text 346 Declarations 351 Primitive instances Module and generated instantiation 353 UDP declaration and instantiation 355 355 Behavioral statements 359 Specify section 365 Expressions General 370 373 Index
  15. Preface The Verilog language is a hardware description language that provides a means of specifying a digital system at a wide range of levels of abstraction. The language sup- ports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural abstractions. The language includes hierarchical constructs, allowing the designer to control a description’s complexity. Verilog was originally designed in the winter of 1983/84 as a proprietary verifica- tion/simulation product. Later, several other proprietary analysis tools were developed around the language, including a fault simulator and a timing analyzer. More recently, Verilog has also provided the input specification for logic and behavioral synthesis tools. The Verilog language has been instrumental in providing consistency across these tools. The language was originally standardized as IEEE standard #1364-1995. It has recently been revised and standardized as IEEE standard #1364-2001. This book presents this latest revision of the language, providing material for the beginning student and advanced user of the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Fur- ther, it is difficult to separate it from a synthesis tool because the semantics of the lan- guage become limited by what a synthesis tool allows in its input specification and produces as an implementation. Where possible, we have stayed away from simulator- and synthesis-specific details and concentrated on design specification. But, we have included enough information to be able to write working executable models.
  16. The Verilog Hardware Description Language xvi The book takes a tutorial approach to presenting the language. Indeed, we start with a tutorial introduction that presents, via examples, the major features of the lan- guage and the prevalent styles of describing systems. We follow this with a detailed presentation on using the language for synthesizing combinational and sequential sys- tems. We then continue with a more complete discussion of the language constructs. Our approach is to provide a means of learning by observing the examples and doing exercises. Numerous examples are provided to allow the reader to learn (and re- learn!) easily by example. It is strongly recommended that you try the exercises as early as possible with the aid of a Verilog simulator. The examples shown in the book are available in electronic form on the enclosed CD. Also included on the CD is a simulator. The simulator is limited in the size of description it will handle. The majority of the book assumes a knowledge of introductory logic design and software programming. As such, the book is of use to practicing integrated circuit design engineers, and undergraduate and graduate electrical or computer engineering students. The tutorial introduction is organized in a manner appropriate for use with a course in introductory logic design. A separate appendix, keyed into the tutorial introduction, provides solved exercises that discuss common errors. The book has also been used for courses in introductory and upper level logic and integrated circuit design, computer architecture, and computer-aided design (CAD). It provides com- plete coverage of the language for design courses, and how a simulator works for CAD courses. For those familiar with the language, we provide a preface that covers most of the new additions to the 2001 language standard. The book is organized into eleven chapters and eight appendices. The first part of the book contains a tutorial introduction to the language which is followed by a chap- ter on its use for logic synthesis. The second part of the book, Chapters 3 through 6, provide a more rigorous presentation of the language’s behavioral, hierarchical, and logic level modeling constructs. The third part of the book, Chapters 7 through 11, covers the more specialized topics of cycle-accurate modeling, timing and event driven simulation, user-defined primitives, and switch level modeling. Chapter 11 suggests two major Verilog projects for use in a university course. One appendix pro- vides tutorial discussion for beginning students. The others are reserved for the dryer topics typically found in a language manual; read those at your own risk. Have fun designing great systems… always, Donald E. Thomas Philip R. Moorby March 2002
  17. From the Old to the New This book as been updated so that the new features of IEEE Std. 1364-2001 are always used even though the “old ways” of writing Verilog (i.e. IEEE Std. 1364-1995) are still valid. In this preface, we show a few side-be-side examples of the old and new. Thus, this section can stand as a short primer on many of the new changes, or as a ref- erence for how to read “old code.” Throughout this preface, cross references are made to further discussion in the earlier parts of the book. However, not all changes are illustrated in this preface. Ports, Sensitivity Lists, and Parameters Port declarations can now be made in “ANSI C” style as shown in Example P.1. In the old style, the port list following the module name could only contain the identifi- ers; the actual declarations were done in separate statements. Additionally, only one declaration could be made in one statement. Now, the declarations can be made in the opening port list and multiple declarations can be made at the same time. Multiple declarations are illustrated in the declaration of eSeg being an “output reg” in the new standard; previously this took two statements as shown on the right of the example (See Section 5.1). This style of declaration also applies to user defined primitives (See chapter 9). These two module descriptions are equivalent.
  18. The Verilog Hardware Description Language xviii module binaryToESeg_Behavioral module binaryToESeg_Behavioral (eSeg, A, B, C, D); (output reg eSeg, input A, B, C, D); output eSeg; input A, B, C, d; always @ (A, B, C, D) begin reg eSeg; eSeg = 1; always @ (A or B or C or D) if(~A & D) eSeg = 0; begin eSeg = 1; if(~A & B & ~C) if (~A & D) eSeg = 0; if(~B & ~C & D) eSeg = 0; eSeg = 0; if (~A & B & ~C) end eSeg = 0; endmodule if (~B & ~C & D) eSeg = 0; Example P.1 2001 Standard (Left); end Previous 1995 (Right) endmodule Example P.1 also shows a simpler way module binaryToESeg_Behavioral to describe sensitivity lists. Previously, the (output reg eSeg, list was an or-separated list of identifiers input A, B, C, D); as shown on the right of the figure. Now, the list can be comma-separated (See always @(*) begin Section 4.2.1). Additionally, if the intent eSeg = 1; is to describe a combinational circuit using if(~A & D) an always block, the explicit sensitivity list eSeg = 0; can replaced with a @(*) as illustrated in if(~A & B & ~C) Example P.2. The module descriptions in eSeg = 0; Examples P.1 and P.2 describe equivalent if(~B & ~ C & D ) functionality. (See Section 2.3.1.) eSeg = 0; end If the module is parameterized, then endmodule the list of parameters is introduced and declared before the port list so that some Example P.2 Sensitivity List Using @(*) of the port specifications can be parame- terized. (See Section 5.2.) This is illus- trated in Example P.3. The new standard also allows for parameters to be over-ridden by name. The old style of instantiating module xorx of Example P.3 would be xorx #(7, 12) x1(a,b,c); where the new value of width is 7 and delay is 12. With the new style, individual parameters can be overridden —
  19. xix module xorx module xorx (xout, xin1, xin2); #(parameter width = 4, parameter width = 4, delay = 10) delay = 10; (output [1:width] xout, output [1:width] xout; input [1:width] xin1,xin2); input [1:width] xin1,xin2; assign #(delay) assign #(delay) xout = xin1 ^ xin2; xout = xin1 ^ xin2; endmodule endmodule Example P.3 Parameter Definition with 2001 Standard (Left) and 1995 (Right) xorx #(.delay(8)) x2 (a,b,c); where delay is changed to 8 and width remains at 4. Functions and tasks may also be declared using the combined port and declaration style. Using the 1995 style, a function with ports would be defined as function [11:0] multiply; input [5:0] a, b; endfunction The new 2001 style allows the definition within the port list; declarations may be of any type (See Section 3.5). function [11:0] multiply (input [5:0] a, b); endfunction Other Changes Many of the other changes are illustrated throughout the book. They are referenced here. Functions may now be declared recursive, constant, and signed (Section 3.5). Tasks may now be declared automatic (Section 3.5). Initial values may now be specified in declarations (See Section 1.4.1). Implicit net declarations are now applied to continuous assignments (Section 6.3). Also, they may now be disabled (Section 6.2.3) with keyword none. Variable part-selects (Section 3.2).
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