UNIVERSITY OF INFORMATION TECHNOLOGY
The VHDL Hardware Description Language
ThS. Le Hoai Nghia
nghialh@uit.edu.vn
February 2009
The VHDL Hardware Description Language – p. 1/44
Why HDLs?
The VHDL Hardware Description Language – p. 2/44
Why HDLs?
The VHDL Hardware Description Language – p. 3/44
Why HDLs?
The VHDL Hardware Description Language – p. 4/44
Two Separate but Equal Languages
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VHDL: Hierarchical Models
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Basic VHDL: Full Adder
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VHDL: Two-bit Counter
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Four-to-one multiplexer: when...else
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Four-to-one mux: with...select
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Three-to-eight Decoder
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Priority Encoder
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Integer Arithmetic
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A Very Simple ALU
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Arithmetic Comparison
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Generate: Ripple-carry adder
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Basic Flip-Flop
The VHDL Hardware Description Language – p. 17/44
Flip-Flop with Synchronous Reset
The VHDL Hardware Description Language – p. 18/44
Four-bit binary counter
The VHDL Hardware Description Language – p. 19/44
Eight-bit serial in/out shift register
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A small RAM
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A small ROM
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Rocket Science: FSMs
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Structure of FSMs in VHDL
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The Traffic Light Controller
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FSM for the Traffic Light Controller
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Traffic Light Controller in VHDL (1)
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Traffic Light Controller in VHDL (2)
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Traffic Light Controller in VHDL (3)
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Traffic Light Controller in VHDL (4)
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Traffic Light Controller in VHDL (5)
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Ten Commandments of VHDL
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I: Thou Shalt Design Before Coding
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II: Thou Shalt be Synchronous
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III: Thou Shalt Be Sensitive
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III: Thou Shalt Be Sensitive
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IV:Thou Shalt Assign All Outputs
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“Default” values are convenient
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V: Thou Shalt Enumerate States
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VI:
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VII: Thou Shalt Avoid Async
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VIII: Thou Shalt Have One Version
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IX: Thou Shalt Not Test For X Or Z
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X: Thou Shalt Not Specify Delays
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