ECE574: VHDL and Verilog Modeling and Synthesis 12/08/10 1
ECE 574: Modeling and Synthesis of Digital Systems using Verilog
and VHDL - Fall 2010
Final Exam – Verilog (6.00 to 8.30)
SOLUTIONS
This exam is in two parts.
• The first part is closed book (no books or notes allowed).
• The second part is open book (books and notes are allowed).
Read each question carefully.
Use a standard and consistent coding style.
Try and answer each question - if you consider any question to be ambiguous
then state any assumptions you make.
NAME: ___________________________
ECE Box: ________________________
ECE574: VHDL and Verilog Modeling and Synthesis 12/08/10 2
Part 1: Closed Book (No Books or Notes allowed)
Question 1 [25 marks]: A state machine used in a process control system has 3 states. It has
a clock and an asynchronous (active high) reset signal, one input called sensor and one output
called valve. The valve output is high in state S1 or S2. The next state/output table is:
Current State sensor
valve
0 1
S0 S0 S1 0
S1 S1 S2 1
S2 S0 S0 1
S*
Draw a state diagram of the state machine.
Write a synthesizable description of this controller. Use a standard two always statement
style. Describe the output logic using a separate assign statement.
ECE574: VHDL and Verilog Modeling and Synthesis 12/08/10 3
Question 2 [20 marks]: Write the Verilog synthesizable module description of a counter
with an asynchronous reset (active high) signal. The counter should count from 7 to 77 on a
negative edge of the clock and then restart at 7.
ECE574: VHDL and Verilog Modeling and Synthesis 12/08/10 4
Question 3 [20 marks]: An FPGA running off its own local 100MHz oscillator is connected
to a GPS device in another system with its own clock. The GPS device generates a 1PPS (one
pulse per second) signal that is high for approximately 10us in duration that it sends to the
FPGA.
It is necessary for the FPGA to generate a single 10ns pulse each time it detects the 1PPS
pulse.
Write a synthesizable module for the FPGA that will convert the 10us pulse from the GPS
device clock domain into the 10ns pulse inside the FPGA. The start of the module description
is provided:
module gps_pps (
input clk,
input pps_long,
output pps_short
);
ECE574: VHDL and Verilog Modeling and Synthesis 12/08/10 5
Question 4 [35 marks]: Write a Verilog model of an SRAM memory device with the
following specifications:
Address bus - 9 bits
Data bus - 8 bits
Active low control signals: CE, OE, WE
Read operation (CE and OE valid):
In the model, output the correct data only after an access time of tacc from OE and CE.
Write operation (CE and WE valid - write data on the rising edge of WE)
In the model check that the address bus is stable for taddr and the data bus is stable for tsetup
before the rising edge of WE.
If they do not meet these requirements then issue appropriate error messages.
Use parameters for the access, address, and setup times with default times of 50, 70, and 25
ns.
Example solution shown on next page: minor variations are OK.