VHDL
- VHDL laø ngoân ngöõ moâ taû phaàn cöùng.
-VHDL vieát taét cuûa VHSIC (Very High Speed Integrated
Circuit) Hardware Description Language
- VHDL khoâng phaân bieät chöõ vieát hoa vaø chöõ thöôøng.
databus Databus DataBus DATABUS
- VHDL laø ngoân ngöõ “ñònh daïng töï do”.
if (a=b) then
if (a=b) then
if (a =
b) then
Basic Design Methodology
Requirements
SimulateRTL Model
Gate-level
Model
Synthesize
Simulate Test Bench
ASIC or FPGA Place & Route
Timing
Model Simulate
Thuaät ngöõ COMPONENT:
- Laø khaùi nieäm trung taâm moâ taû phaàn cöùng baèng VHDL ñeå bieåu
dieãn caùc caáp thieát keá töø coång ñôn giaûn ñeán 1 heä thoáng phöùc taïp.
- Moâ taû component bao goàm ENTITY vaø ARCHITECTURE.
-Moâ taû component bao goàm ENTITY vaø ARCHITECTURE.
d0
d1 y
sel
mux2to1
a
bz
nand2
Maõ VHDL cô baûn
LIBRARY
khai baùo thö vieän
ENTITY
thöïc theå
ARCHITECTURE
kieán truùc
Ví duï: Maõ VHDL moâ taû component NAND 2 ngoõ vaøo
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a: IN STD_LOGIC;
b: IN STD_LOGIC;
z: OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z<= aNAND b;
END model;
a
bz
