VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY
UNIVERSITY OF SCIENCE
LÊ THỊ LINH AN
A SOFT ERROR TOLERANT SRAM DESIGN
IN 130NM CMOS TECHNOLOGY
Specialization: Electronic Engineering – Microelectronics Major
Code: 60 52 70
MASTER DEGREE THESIS
ELECTRONICS ENGINEERING – MICROELECTRONICS
SUPERVISOR
Dr. BÙI TRỌNG TÚ
Ho Chi Minh City, 2010
ACKNOWLEDGEMENTS
It is my pleasure to thank all the people who made this thesis possible.
First of all, I would like to sincerely express my appreciation to my advisor, Dr.
Bui Trong Tu, for his tremendous support, valuable guidance and constant
encouragement during my studies. His technical advice made my master’s studies
a meaningful learning experience.
I am also grateful to Prof. Dang Luong Mo, Prof. Nguyen Huu Phuong, and Dr.
Huynh Huu Thuan, who are the managers of this Microelectronics Master
program. This is really an interesting course with enthusiastic and devoted
professors, who are the experts in the IC industry.
I also wish to thank my colleagues in TCAM team for all helpful discussion and
valuable advice during my study. Appreciation is expressed for Silicon Design
Solutions Company who have supported me about financial and let me join in this
Master course during my work.
Finally, my special thanks to my family who have always been with me
throughout the difficulties and challenges of my master study.
Ho Chi Minh City, November 2010
Le Thi
LinhAn
ABSTRACT
Soft error is a great concern for microelectronics circuits today. With the advanced
development in CMOS technologies, VLSI circuits are becoming more sensitive to
external noise sources, especially radiation particle strikes, which are the cause of
soft error. Soft errors are random and do not cause the permanent failure.
However, it causes the corruption of stored information, which could turn to the
failure in functionality of the circuits.
Meanwhile, the demand for a higher reliability of electronics applications is
always a non-stop requirement. There are a lot of critical applications that need the
extreme exactly in circuit functionality, such as the circuits used in space or
biomedical equipment, as well as the military electronics and so on.
Generally, soft errors in memories attracted more attention than soft errors in logic
circuit. In addition, memories play an important part in modern system. Because of
the high integration of storage cells, a large memory is more sensitive to particle
strikes than logic. Due to that motivation, this thesis focuses to study about soft
errors in memories.
The thesis goes through the background knowledge of soft errors and its
mitigation techniques. Then, a SRAM design with additional soft error tolerant
feature will be presented. The SRAM is designed in 130nm CMOS technology,
using circuit hardening and error correcting code techniques to mitigate the soft
error effect. The soft error tolerant level is verified by some simulations. Not only
focus on the soft error tolerant circuits, a whole SRAM architecture will be shown
in detail, from circuit to physical implementation. The verification and simulation
results are also included.
TABLE OF CONTENTS
Acknowledgement
Abstract
Table of contents
Abbreviations
List of tables
List of figures
CHAPTER 1 - INTRODUCTION .................................................................................... 1
1.1. Problem and motivation ............................................................................................. 1
1.2. Contribution of the thesis ........................................................................................... 2
1.3. Thesis organization .................................................................................................... 2
CHAPTER 2 - BACKGROUND ....................................................................................... 4
2.1. Soft errors in semiconductor device ........................................................................... 4
2.1.1. Radiation sources ................................................................................................. 4
2.2. Soft errors occurrence mechanism ............................................................................. 5
2.3. Soft errors mitigation techniques ............................................................................... 6
2.3.1. Device level techniques ....................................................................................... 6
2.3.2. Circuit level techniques ....................................................................................... 7
2.3.3. Block level techniques ......................................................................................... 7
CHAPTER 3 – SOFT ERROR TOLERANT SRAM DESIGN ................................... 10
3.1. SRAM specification ................................................................................................. 10
3.1.1. General information ........................................................................................... 10
3.1.2. Floorplan ............................................................................................................ 11
3.1.4. Operation brief description ................................................................................ 12
3.2. SRAM detail design ................................................................................................. 14
3.2.1. SRAM cell architecture ..................................................................................... 14
3.2.2. Replica path for Read operation ........................................................................ 15
3.2.3. Internal clock generator ..................................................................................... 17
3.2.4. Write circuit ....................................................................................................... 19
3.2.5. Decoder .............................................................................................................. 19
3.2.6. Input/output latches .......................................................................................... 21
3.3. Error detecting and correcting (EDC) block ............................................................ 22
3.3.1. Hamming code algorithm .................................................................................. 23
3.3.2. EDC block implementation ............................................................................... 24
3.3.3. EDC detail architecture ...................................................................................... 26
CHAPTER 4 – DESIGN SIMULATION AND VERIFICATION .............................. 37
4.1. SRAM cell simulation .............................................................................................. 37
4.1.1. SRAM cell simulation to find device size ......................................................... 37
4.1.2. SRAM cell characteristic summary ................................................................... 42
4.1.3. Static noise margin comparison ......................................................................... 43
4.1.4. SRAM cell capacitance ...................................................................................... 43
4.2. Soft error tolerant simulation ................................................................................... 44
4.2.1. Verification methodology .................................................................................. 44
4.2.2. Critical charge simulation .................................................................................. 45
4.2.3. Simulation results .............................................................................................. 46
4.2.4. Conclusion ......................................................................................................... 49
4.3. Post-layout simulation .............................................................................................. 50
4.3.1. Simulation setup ................................................................................................ 50