Design and Implementation
of VLSI Systems
Lecture 06
Thuan Nguyen
Faculty of Electronics and Telecommunications,
University of Science, VNU HCMUS
Spring 2011
1
INTRODUCTION
The delay of a logic gate:
C: load capacitance
t ∝ 𝐶
𝐼∆𝑉 I: output current
∆𝑉: output voltage swing
2
nMOS provides more current than pMOS for the same size
and capacitance
Static CMOS requires both nMOS and pMOS on each
input.
All the node voltages in static CMOS must transition
between 0 and VDD propagation delay + power
consumption.
Circuit families
LECTURE 06: CIRCUIT CHARACTERIZATION &
PERFORMANCE ESTIMATION
Static CMOS
1
Ratioed Circuits
2
Dynamic Circuits
3
Pass-transistor Circuits
4
3
LECTURE 06: CIRCUIT CHARACTERIZATION &
PERFORMANCE ESTIMATION
Static CMOS
1
Ratioed Circuits
2
Dynamic Circuits
3
Pass-transistor Circuits
4
4
OUTLINE
Bubble Pushing
Compound Gates
Logical Effort Example
Input Ordering
Asymmetric Gates
Skewed Gates
Best P/N ratio
5
