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library ieee;
use ieee.std_logic_1164.all;
entity CAU5 is
port ( CLK : IN std_logic;
Q : BUFFER std_logic_vector(2 downto 0));
end CAU5;
architecture THI of CAU5 is
component T_FF
port ( T, CK, Pr, Cl: IN std_logic;
Q: OUT std_logic);
end component;
signal Z, ONE, ZERO: std_logic;
begin
ONE <= ’1’; ZERO <= ’0’;
Z <= not Q(2) and Q(1) and not Q(0);
u0: T_FF port map (ONE, CLK, Z, ZERO, Q(0));
u1: T_FF port map (ONE, Q(0), Z, ZERO, Q(1));
u2: T_FF port map (ONE, Q(1), Z, ZERO, Q(2));
end THI;
e
ntity CAU6 is
port ( A, B: IN std_logic;
F: OUT std_logic);
end CAU6;
architecture THI of CAU6 is
component NAND2
port (x, y: IN std_logic;
z: OUT std_logic);
end component;
s
ignal C1,C2,C3,C4: std
_
logic;
begin
u1: NAND2 port map (A, A, C1);
u2: NAND2 port map (C1, B, C2);
u3: NAND2 port map (B, B, C3);
u4: NAND2 port map (C3, A, C4);
u5: NAND2 port map (C2, c4, F);
end THI;