Design and Implementation
of VLSI Systems
Lecture 05
Thuan Nguyen
Faculty of Electronics and Telecommunications,
University of Science, VNU HCMUS
Spring 2011
1
LECTURE 05: CIRCUIT CHARACTERIZATION &
PERFORMANCE ESTIMATION
2
Delay Estimation
1
Logical Effort for Delay Estimation
2
Power Estimation
3
Interconnect and Wire Engineering
4
Scaling Theory
5
3
Delay Estimation
1
Logical Effort for Delay Estimation
2
Power Estimation
3
Interconnect and Wire Engineering
4
Scaling Theory
5
LECTURE 05: CIRCUIT CHARACTERIZATION &
PERFORMANCE ESTIMATION
INTRODUCTION
Critical paths are those which require attention
to timing details
Timing analyzer is a design tool that
automatically finds the slowest path in a logic
design
Altera: Classic Timing Analyzer, TimeQuest Timing
Analyzer
Synopsys: PrimeTime
The critical paths can be affected at four main
levels
The architecture/ microarchitecture level
The logic level
The circuit level
The layout level 4
DELAY DEFINITIONS
tpdr: rising propagation delay
Max time: From input to rising output crossing VDD/2
tpdf: falling propagation delay
Max time: From input to falling output crossing VDD/2
tpd: average propagation delay. tpd = (tpdr + tpdf)/2
tcdr: rising contamination (best-case) delay
Min time: From input to rising output crossing VDD/2
tcdf: falling contamination (best-case) delay
Min time: From input to falling output crossing VDD/2
tcd: average contamination delay. tcd = (tcdr + tcdf)/2
tr: rise time
From output crossing 0.2 VDD to 0.8 VDD
tf: fall time
From output crossing 0.8 VDD to 0.2 VDD
5