MC9S08QE32 - MC9S08QE16: Reference Manual

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MC9S08QE32 MC9S08QE16 Reference Manual Related Documentation: HCS08 Microcontrollers • MC9S08QE32 (Data Sheet) Contains pin assignments and diagrams, all electrical specifications, and mechanical drawing outlines. Find the most current versions of all documents at: http://www.freescale.com MC9S08QE32RM Rev. 2 5/2009 freescale.com
MC9S08QE32 Features Features – ACMPx — Two analog comparators with selectable interrupt • 8-Bit HCS08 Central Processor Unit (CPU) on rising, falling, or either edge of comparator output; – Up to 50.33 MHz HCS08 CPU at 3.6V to 2.4V, 40 MHz CPU compare option to fixed internal bandgap reference voltage; at 2.4 V to 2.1 V and 20 MHz CPU at 2.1 V to 1.8 V across outputs can be optionally routed to TPM module; operation in temperature range of –40 °C to 85 °C stop3 – HC08 instruction set with added BGND instruction – SCIx — Two serial communications interface modules with – Support for up to 32 interrupt/reset sources optional 13-bit break; full duplex non-return to zero (NRZ); • On-Chip Memory LIN master extended break generation; LIN slave extended – Flash read/program/erase over full operating voltage and break detection; wake up on active edge temperature – SPI — One serial peripheral interface; full-duplex or – Random-access memory (RAM) single-wire bidirectional; double-buffered transmit and – Security circuitry to prevent unauthorized access to RAM and receive; master or slave mode; MSB-first or LSB-first shifting flash contents – IIC — One IIC; up to 100 kbps with maximum bus loading; • Power-Saving Modes multi-master operation; programmable slave address; – Two very low power stop modes interrupt driven byte-by-byte data transfer; supports broadcast – Reduced power wait mode mode and 10-bit addressing – Peripheral clock enable register can disable clocks to unused – TPMx — One 6-channel (TPM3) and two 3-channel (TPM1 modules, thereby reducing currents; allows clocks to remain and TPM2); selectable input capture, output compare, or enabled to specific peripherals in stop3 mode buffered edge- or center-aligned PWM on each channel – Very low power external oscillator that can be used in run, – RTC — (Real-time counter) 8-bit modulus counter with wait, and stop modes to provide accurate clock source to real binary or decimal based prescaler; external clock source for time counter precise time base, time-of-day, calendar or task scheduling – 6 μs typical wakeup time from stop3 mode functions; free running on-chip low power oscillator (1 kHz) • Clock Source Options for cyclic wakeup without external components; runs in all – Oscillator (XOSCVLP) — Loop-control Pierce oscillator; MCU modes crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or • Input/Output 1 MHz to 16 MHz – 40 GPIOs, including 1 output-only pin and 1 input-only pin – Internal clock source (ICS) — Internal clock source module – 16 KBI interrupts with selectable polarity containing a frequency-locked-loop (FLL) controlled by – Hysteresis and configurable pullup device on all input pins; internal or external reference; precision trimming of internal configurable slew rate and drive strength on all output pins reference allows 0.2% resolution and 2% deviation over • Package Options temperature and voltage; supports CPU frequencies from – 48-pin QFN, 44-pin LQFP, 32-pin LQFP, 28-pin SOIC 4 kHz to 50.33 MHz • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-voltage warning with interrupt. – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset – Flash block protection • Development Support – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus three breakpoints in on-chip debug module) – On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes; eight deep FIFO for storing change-of-flow addresses and event-only data; debug module supports both tag and force breakpoints • Peripherals – ADC — 10-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V
MC9S08QE32 MCU Series Reference Manual Covers: MC9S08QE32 MC9S08QE16 MC9S08QE32 Rev. 2 5/2009
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Revision Revision Description of Changes Number Date 1 7/2/2008 Initial public release. Changed VDDAD to VDDA, VSSAD to VSSA. Updated Figure 4-2 and Figure 4-3. Updated Section 13.1.5, “RTC Clock Gating.” In Chapter 11, “Internal Clock Source (S08ICSV3),” added a note in Section 11.1.5.7, “Stop (STOP) ” updated Figure 11-2 to reflect ICSERCLK is gated off when STOP is high or when ERCLKEN is low. 2 5/5/2009 In Chapter 10, “Analog-to-Digital Converter (S08ADC12V1),” changed VDDA supply references to VDDA; fixed ADCRH:L description for compare operation, including an updates of Section 10.4.5, “Automatic Compare Function” description and ADCRH:L register descriptions (Section 10.3.3, “Data Result High Register (ADCRH) and Section 10.3.4, “Data Result Low Register (ADCRL).”) Reworded Chapter 16, “Timer/Pulse-Width Modulator (S08TPMV3).” This product incorporates SuperFlash® technology licensed from SST. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008-2009. All rights reserved. MC9S08QE32 MCU Series Reference Manual, Rev. 2 6 Freescale Semiconductor
List of Chapters Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 5 Resets, Interrupts, and General System Control . . . . . . . . . . . . . 69 Chapter 6 Parallel Input/Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Chapter 7 Keyboard Interrupt (S08KBIV2) . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chapter 8 Central Processor Unit (S08CPUV4) . . . . . . . . . . . . . . . . . . . . . . 113 Chapter 9 Analog Comparator 3V (ACMPVLPV1). . . . . . . . . . . . . . . . . . . . . 133 Chapter 10 Analog-to-Digital Converter (S08ADC12V1) . . . . . . . . . . . . . . . 139 Chapter 11 Internal Clock Source (S08ICSV3) . . . . . . . . . . . . . . . . . . . . . . . 167 Chapter 12 Inter-Integrated Circuit (S08IICV2) . . . . . . . . . . . . . . . . . . . . . . . 181 Chapter 13 Real-Time Counter (S08RTCV1) . . . . . . . . . . . . . . . . . . . . . . . . . 199 Chapter 14 Serial Communications Interface (S08SCIV4) . . . . . . . . . . . . . . 209 Chapter 15 Serial Peripheral Interface (S08SPIV3). . . . . . . . . . . . . . . . . . . . 229 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) . . . . . . . . . . . . . . . . 245 Chapter 17 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Chapter 18 Debug Module (S08DBGV3) (64K) . . . . . . . . . . . . . . . . . . . . . . . 282 MC9S08QE32 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor 7
Contents Section Number Title Page Chapter 1 Device Overview 1.1 Devices in the MC9S08QE32 Series ..............................................................................................19 1.2 MCU Block Diagram ......................................................................................................................20 1.3 System Clock Distribution ..............................................................................................................21 Chapter 2 Pins and Connections 2.1 Device Pin Assignment ...................................................................................................................23 2.2 Recommended System Connections ...............................................................................................28 2.2.1 Power ................................................................................................................................29 2.2.2 Oscillator ...........................................................................................................................29 2.2.3 RESET Pin ........................................................................................................................29 2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................30 2.2.5 General-Purpose I/O (GPIO) and Peripheral Ports ...........................................................31 Chapter 3 Modes of Operation 3.1 Introduction .....................................................................................................................................35 3.2 Features ...........................................................................................................................................35 3.3 Run Mode ........................................................................................................................................35 3.3.1 Low Power Run Mode (LPRun) .......................................................................................35 3.4 Active Background Mode ...............................................................................................................36 3.5 Wait Mode .......................................................................................................................................37 3.5.1 Low-Power Wait Mode (LPWait) .....................................................................................38 3.6 Stop Modes ......................................................................................................................................38 3.6.1 Stop2 Mode .......................................................................................................................39 3.6.2 Stop3 Mode .......................................................................................................................40 3.6.3 Active BDM Enabled in Stop Mode .................................................................................41 3.6.4 LVD Enabled in Stop Mode ..............................................................................................42 3.6.5 Stop modes in Low Power Run Mode ..............................................................................42 3.7 Mode selection ................................................................................................................................42 3.7.1 On-Chip Peripheral Modules in Stop and Low Power Modes .........................................46 Chapter 4 Memory 4.1 MC9S08QE32 Series Memory Map ...............................................................................................47 4.2 Reset and Interrupt Vector Assignments .........................................................................................48 4.3 Register Addresses and Bit Assignments ........................................................................................49 MC9S08QE32 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor 9
4.4 RAM ................................................................................................................................................56 4.5 Flash ................................................................................................................................................56 4.5.1 Features .............................................................................................................................57 4.5.2 Program and Erase Times .................................................................................................57 4.5.3 Program and Erase Command Execution .........................................................................58 4.5.4 Burst Program Execution ..................................................................................................59 4.5.5 Access Errors ....................................................................................................................61 4.5.6 Flash Block Protection ......................................................................................................61 4.5.7 Vector Redirection ............................................................................................................62 4.6 Security ............................................................................................................................................62 4.7 Flash Registers and Control Bits .....................................................................................................63 4.7.1 Flash Clock Divider Register (FCDIV) ............................................................................64 4.7.2 Flash Options Register (FOPT and NVOPT) ....................................................................65 4.7.3 Flash Configuration Register (FCNFG) ...........................................................................66 4.7.4 Flash Protection Register (FPROT and NVPROT) ..........................................................66 4.7.5 Flash Status Register (FSTAT) ..........................................................................................67 4.7.6 Flash Command Register (FCMD) ...................................................................................68 Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction .....................................................................................................................................69 5.2 Features ...........................................................................................................................................69 5.3 MCU Reset ......................................................................................................................................69 5.4 Computer Operating Properly (COP) Watchdog .............................................................................70 5.5 Interrupts .........................................................................................................................................71 5.5.1 Interrupt Stack Frame .......................................................................................................72 5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................72 5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................73 5.6 Low-Voltage Detect (LVD) System ................................................................................................75 5.6.1 Power-On Reset Operation ...............................................................................................75 5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................75 5.6.3 Low-Voltage Detection (LVD) Interrupt Operation ..........................................................75 5.6.4 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................75 5.7 Peripheral Clock Gating ..................................................................................................................75 5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................76 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................76 5.8.2 System Reset Status Register (SRS) .................................................................................78 5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................79 5.8.4 System Options Register 1 (SOPT1) ................................................................................80 5.8.5 System Options Register 2 (SOPT2) ................................................................................81 5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................82 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................83 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................84 5.8.9 System Power Management Status and Control 3 Register (SPMSC3) ...........................85 5.8.10 System Clock Gating Control 1 Register (SCGC1) ..........................................................86 MC9S08QE32 MCU Series Reference Manual, Rev. 2 10 Freescale Semiconductor
5.8.11 System Clock Gating Control 2 Register (SCGC2) ..........................................................87 Chapter 6 Parallel Input/Output Control 6.1 Port Data and Data Direction ..........................................................................................................89 6.2 Pullup, Slew Rate, and Drive Strength ............................................................................................90 6.2.1 Port Internal Pullup Enable ...............................................................................................90 6.2.2 Port Slew Rate Enable ......................................................................................................90 6.2.3 Port Drive Strength Select ................................................................................................90 6.3 Pin Behavior in Stop Modes ............................................................................................................91 6.4 Parallel I/O and Pin Control Registers ............................................................................................91 6.4.1 Port A Registers ................................................................................................................92 6.4.2 Port A Drive Strength Selection Register (PTADS) .........................................................94 6.4.3 Port B Registers ................................................................................................................95 6.4.4 Port C Registers ................................................................................................................97 6.4.5 Port D Registers ..............................................................................................................100 6.4.6 Port E Registers ..............................................................................................................102 Chapter 7 Keyboard Interrupt (S08KBIV2) 7.1 Introduction ...................................................................................................................................105 7.1.1 KBI Clock Gating ...........................................................................................................105 7.1.2 Features ...........................................................................................................................107 7.1.3 Modes of Operation ........................................................................................................107 7.1.4 Block Diagram ................................................................................................................107 7.2 External Signal Description ..........................................................................................................108 7.3 Register Definition ........................................................................................................................109 7.3.1 KBI Interrupt Status and Control Register (KBIxSC) ....................................................109 7.3.2 KBI Interrupt Pin Select Register (KBIxPE) ..................................................................110 7.3.3 KBI Interrupt Edge Select Register (KBIxES) ...............................................................110 7.4 Functional Description ..................................................................................................................110 7.4.1 Edge Only Sensitivity ..................................................................................................... 111 7.4.2 Edge and Level Sensitivity .............................................................................................111 7.4.3 Pullup/Pulldown Resistors .............................................................................................. 111 7.4.4 Keyboard Interrupt Initialization ....................................................................................111 Chapter 8 Central Processor Unit (S08CPUV4) 8.1 Introduction ...................................................................................................................................113 8.1.1 Features ...........................................................................................................................113 8.2 Programmer’s Model and CPU Registers .....................................................................................114 8.2.1 Accumulator (A) .............................................................................................................114 8.2.2 Index Register (H:X) ......................................................................................................114 8.2.3 Stack Pointer (SP) ...........................................................................................................115 8.2.4 Program Counter (PC) ....................................................................................................115 MC9S08QE32 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor 11
8.2.5 Condition Code Register (CCR) .....................................................................................115 8.3 Addressing Modes .........................................................................................................................117 8.3.1 Inherent Addressing Mode (INH) ...................................................................................117 8.3.2 Relative Addressing Mode (REL) ..................................................................................117 8.3.3 Immediate Addressing Mode (IMM) ..............................................................................117 8.3.4 Direct Addressing Mode (DIR) ......................................................................................117 8.3.5 Extended Addressing Mode (EXT) ................................................................................118 8.3.6 Indexed Addressing Mode ..............................................................................................118 8.4 Special Operations .........................................................................................................................119 8.4.1 Reset Sequence ...............................................................................................................119 8.4.2 Interrupt Sequence ..........................................................................................................119 8.4.3 Wait Mode Operation ......................................................................................................120 8.4.4 Stop Mode Operation ......................................................................................................120 8.4.5 BGND Instruction ...........................................................................................................121 8.5 HCS08 Instruction Set Summary ..................................................................................................122 Chapter 9 Analog Comparator 3V (ACMPVLPV1) 9.1 Introduction ...................................................................................................................................133 9.1.1 ACMP Configuration Information ..................................................................................133 9.1.2 ACMP/TPM Configuration Information ........................................................................133 9.1.3 ACMP Clock Gating .......................................................................................................133 9.1.4 Interrupt Vectors .............................................................................................................134 9.1.5 Features ...........................................................................................................................135 9.1.6 Modes of Operation ........................................................................................................135 9.1.7 Block Diagram ................................................................................................................135 9.2 External Signal Description ..........................................................................................................136 9.3 Register Definition ........................................................................................................................136 9.3.1 Status and Control Register (ACMPxSC) .......................................................................136 9.4 Functional Description ..................................................................................................................137 9.5 Interrupts .......................................................................................................................................137 Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.1 Introduction ...................................................................................................................................139 10.1.1 ADC Clock Gating ..........................................................................................................139 10.1.2 Module Configurations ...................................................................................................140 10.1.3 Features ...........................................................................................................................143 10.1.4 ADC Module Block Diagram .........................................................................................143 10.2 External Signal Description ..........................................................................................................144 10.2.1 Analog Power (VDDA) ....................................................................................................145 10.2.2 Analog Ground (VSSA) ...................................................................................................145 10.2.3 Voltage Reference High (VREFH) ...................................................................................145 10.2.4 Voltage Reference Low (VREFL) ....................................................................................145 10.2.5 Analog Channel Inputs (ADx) ........................................................................................145 MC9S08QE32 MCU Series Reference Manual, Rev. 2 12 Freescale Semiconductor
10.3 Register Definition ........................................................................................................................145 10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................145 10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................147 10.3.3 Data Result High Register (ADCRH) .............................................................................148 10.3.4 Data Result Low Register (ADCRL) ..............................................................................148 10.3.5 Compare Value High Register (ADCCVH) ....................................................................149 10.3.6 Compare Value Low Register (ADCCVL) .....................................................................149 10.3.7 Configuration Register (ADCCFG) ................................................................................149 10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................151 10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................152 10.3.10Pin Control 3 Register (APCTL3) ..................................................................................153 10.4 Functional Description ..................................................................................................................154 10.4.1 Clock Select and Divide Control ....................................................................................154 10.4.2 Input Select and Pin Control ...........................................................................................155 10.4.3 Hardware Trigger ............................................................................................................155 10.4.4 Conversion Control .........................................................................................................155 10.4.5 Automatic Compare Function .........................................................................................158 10.4.6 MCU Wait Mode Operation ............................................................................................159 10.4.7 MCU Stop3 Mode Operation ..........................................................................................159 10.4.8 MCU Stop2 Mode Operation ..........................................................................................160 10.5 Initialization Information ..............................................................................................................160 10.5.1 ADC Module Initialization Example .............................................................................160 10.6 Application Information ................................................................................................................162 10.6.1 External Pins and Routing ..............................................................................................162 10.6.2 Sources of Error ..............................................................................................................164 Chapter 11 Internal Clock Source (S08ICSV3) 11.1 Introduction ...................................................................................................................................167 11.1.1 External Oscillator ..........................................................................................................167 11.1.2 Stop2 Mode Considerations ............................................................................................167 11.1.3 Features ...........................................................................................................................169 11.1.4 Block Diagram ................................................................................................................169 11.1.5 Modes of Operation ........................................................................................................170 11.2 External Signal Description ..........................................................................................................171 11.3 Register Definition ........................................................................................................................171 11.3.1 ICS Control Register 1 (ICSC1) .....................................................................................172 11.3.2 ICS Control Register 2 (ICSC2) .....................................................................................173 11.3.3 ICS Trim Register (ICSTRM) .........................................................................................174 11.3.4 ICS Status and Control (ICSSC) .....................................................................................174 11.4 Functional Description ..................................................................................................................176 11.4.1 Operational Modes ..........................................................................................................176 11.4.2 Mode Switching ..............................................................................................................178 11.4.3 Bus Frequency Divider ...................................................................................................179 11.4.4 Low Power Bit Usage .....................................................................................................179 MC9S08QE32 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor 13
11.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................179 11.4.6 Internal Reference Clock ................................................................................................179 11.4.7 External Reference Clock ...............................................................................................180 11.4.8 Fixed Frequency Clock ...................................................................................................180 11.4.9 Local Clock .....................................................................................................................180 Chapter 12 Inter-Integrated Circuit (S08IICV2) 12.1 Introduction ...................................................................................................................................181 12.1.1 Module Configuration .....................................................................................................181 12.1.2 IIC Clock Gating .............................................................................................................181 12.1.3 Features ...........................................................................................................................183 12.1.4 Modes of Operation ........................................................................................................183 12.1.5 Block Diagram ................................................................................................................183 12.2 External Signal Description ..........................................................................................................184 12.2.1 SCL — Serial Clock Line ...............................................................................................184 12.2.2 SDA — Serial Data Line ................................................................................................184 12.3 Register Definition ........................................................................................................................184 12.3.1 IIC Address Register (IICA) ...........................................................................................185 12.3.2 IIC Frequency Divider Register (IICF) ..........................................................................185 12.3.3 IIC Control Register (IICC1) ..........................................................................................188 12.3.4 IIC Status Register (IICS) ...............................................................................................188 12.3.5 IIC Data I/O Register (IICD) ..........................................................................................189 12.3.6 IIC Control Register 2 (IICC2) .......................................................................................190 12.4 Functional Description ..................................................................................................................191 12.4.1 IIC Protocol .....................................................................................................................191 12.4.2 10-bit Address .................................................................................................................194 12.4.3 General Call Address ......................................................................................................195 12.5 Resets ............................................................................................................................................195 12.6 Interrupts .......................................................................................................................................195 12.6.1 Byte Transfer Interrupt ....................................................................................................195 12.6.2 Address Detect Interrupt .................................................................................................196 12.6.3 Arbitration Lost Interrupt ................................................................................................196 12.7 Initialization/Application Information ..........................................................................................197 Chapter 13 Real-Time Counter (S08RTCV1) 13.1 Introduction ...................................................................................................................................199 13.1.1 ADC Hardware Trigger ..................................................................................................199 13.1.2 RTC Clock Sources .........................................................................................................199 13.1.3 RTC Modes of Operation ................................................................................................199 13.1.4 RTC Status after Stop2 Wakeup ......................................................................................199 13.1.5 RTC Clock Gating ..........................................................................................................199 13.1.6 Features ...........................................................................................................................201 13.1.7 Modes of Operation ........................................................................................................201 MC9S08QE32 MCU Series Reference Manual, Rev. 2 14 Freescale Semiconductor
13.1.8 Block Diagram ................................................................................................................202 13.2 External Signal Description ..........................................................................................................202 13.3 Register Definition ........................................................................................................................202 13.3.1 RTC Status and Control Register (RTCSC) ....................................................................203 13.3.2 RTC Counter Register (RTCCNT) ..................................................................................204 13.3.3 RTC Modulo Register (RTCMOD) ................................................................................204 13.4 Functional Description ..................................................................................................................204 13.4.1 RTC Operation Example .................................................................................................205 13.5 Initialization/Application Information ..........................................................................................206 Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction ...................................................................................................................................209 14.1.1 SCI Clock Gating ............................................................................................................209 14.1.2 Features ...........................................................................................................................212 14.1.3 Modes of Operation ........................................................................................................212 14.1.4 Block Diagram ................................................................................................................212 14.2 Register Definition ........................................................................................................................215 14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................215 14.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................216 14.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................217 14.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................218 14.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................220 14.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................221 14.2.7 SCI Data Register (SCIxD) .............................................................................................222 14.3 Functional Description ..................................................................................................................222 14.3.1 Baud Rate Generation .....................................................................................................222 14.3.2 Transmitter Functional Description ................................................................................223 14.3.3 Receiver Functional Description ....................................................................................224 14.3.4 Interrupts and Status Flags ..............................................................................................226 14.3.5 Additional SCI Functions ...............................................................................................227 Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1 Introduction ...................................................................................................................................229 15.1.1 SPI Port Configuration Information ...............................................................................229 15.1.2 SPI Clock Gating ............................................................................................................229 15.1.3 Features ...........................................................................................................................231 15.1.4 Block Diagrams ..............................................................................................................231 15.1.5 SPI Baud Rate Generation ..............................................................................................233 15.2 External Signal Description ..........................................................................................................234 15.2.1 SPSCK — SPI Serial Clock ............................................................................................234 15.2.2 MOSI — Master Data Out, Slave Data In ......................................................................234 15.2.3 MISO — Master Data In, Slave Data Out ......................................................................234 15.2.4 SS — Slave Select ..........................................................................................................234 MC9S08QE32 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor 15
15.3 Modes of Operation .......................................................................................................................235 15.3.1 SPI in Stop Modes ..........................................................................................................235 15.4 Register Definition ........................................................................................................................235 15.4.1 SPI Control Register 1 (SPIC1) ......................................................................................235 15.4.2 SPI Control Register 2 (SPIC2) ......................................................................................236 15.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................237 15.4.4 SPI Status Register (SPIS) ..............................................................................................238 15.4.5 SPI Data Register (SPID) ...............................................................................................239 15.5 Functional Description ..................................................................................................................240 15.5.1 SPI Clock Formats ..........................................................................................................240 15.5.2 SPI Interrupts ..................................................................................................................243 15.5.3 Mode Fault Detection .....................................................................................................243 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) 16.1 Introduction ...................................................................................................................................245 16.1.1 ACMP/TPM Configuration Information ........................................................................245 16.1.2 TPM Clock Gating ..........................................................................................................245 16.1.3 TPMV3 Differences from Previous Versions .................................................................246 16.1.4 Migrating from TPMV1 ..................................................................................................249 16.1.5 Features ...........................................................................................................................250 16.1.6 Modes of Operation ........................................................................................................250 16.1.7 Block Diagram ................................................................................................................251 16.2 Signal Description .........................................................................................................................253 16.2.1 Detailed Signal Descriptions ..........................................................................................253 16.3 Register Definition ........................................................................................................................256 16.3.1 TPM Status and Control Register (TPMxSC) ................................................................256 16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................257 16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................258 16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................259 16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................260 16.4 Functional Description ..................................................................................................................262 16.4.1 Counter ............................................................................................................................262 16.4.2 Channel Mode Selection .................................................................................................263 16.5 Reset Overview .............................................................................................................................266 16.5.1 General ............................................................................................................................266 16.5.2 Description of Reset Operation .......................................................................................267 16.6 Interrupts .......................................................................................................................................267 16.6.1 General ............................................................................................................................267 16.6.2 Description of Interrupt Operation .................................................................................267 Chapter 17 Development Support 17.1 Introduction ...................................................................................................................................270 17.1.1 Forcing Active Background ............................................................................................270 MC9S08QE32 MCU Series Reference Manual, Rev. 2 16 Freescale Semiconductor
17.1.2 Module Configuration .....................................................................................................270 17.1.3 Features ...........................................................................................................................271 17.2 Background Debug Controller (BDC) ..........................................................................................271 17.2.1 BKGD Pin Description ...................................................................................................272 17.2.2 Communication Details ..................................................................................................272 17.2.3 BDC Commands .............................................................................................................275 17.2.4 BDC Hardware Breakpoint .............................................................................................278 17.3 Register Definition ........................................................................................................................278 17.3.1 BDC Registers and Control Bits .....................................................................................278 17.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................281 Chapter 18 Debug Module (S08DBGV3) (64K) 18.1 Introduction ...................................................................................................................................282 18.1.1 Features ...........................................................................................................................282 18.1.2 Modes of Operation ........................................................................................................283 18.1.3 Block Diagram ................................................................................................................283 18.2 Signal Description .........................................................................................................................283 18.3 Memory Map and Registers ..........................................................................................................284 18.3.1 Module Memory Map .....................................................................................................284 18.3.2 Register Bit Summary .....................................................................................................285 18.3.3 Register Descriptions ......................................................................................................286 18.4 Functional Description ..................................................................................................................297 18.4.1 Comparator .....................................................................................................................297 18.4.2 Breakpoints .....................................................................................................................297 18.4.3 Trigger Selection .............................................................................................................298 18.4.4 Trigger Break Control (TBC) .........................................................................................298 18.4.5 FIFO ................................................................................................................................302 18.4.6 Interrupt Priority .............................................................................................................303 18.5 Resets ............................................................................................................................................303 18.6 Interrupts .......................................................................................................................................303 MC9S08QE32 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor 17
MC9S08QE32 MCU Series Reference Manual, Rev. 2 18 Freescale Semiconductor
Chapter 1 Device Overview The MC9S08QE32 and MC9S08QE16 are members of the low-cost, low-power, high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.1 Devices in the MC9S08QE32 Series Table 1-1 summarizes the feature set available in the MC9S08QE32 series of MCUs. Table 1-1. MC9S08QE32 Series Features by MCU and Package Feature MC9S08QE32 MC9S08QE16 Flash size (bytes) 32768 16384 RAM size (bytes) 2048 1024 Pin quantity 48 44 32 28 48 44 32 28 ACMP1 yes ACMP2 yes ADC channels 10 DBG yes ICS yes IIC yes IRQ yes KBI 16 16 12 8 16 16 12 8 1 Port I/O 38 34 26 22 38 34 26 22 RTC yes SCI1 yes SCI2 yes SPI yes TPM1 channels 3 TPM2 channels 3 TPM3 channels 6 XOSCVLP yes 1 Port I/O count does not include the input only PTA5/IRQ/TPM1CLK/RESET or the output only PTA4/ACMP1O/BKGD/MS. MC9S08QE32 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor 19
Chapter 1 Device Overview 1.2 MCU Block Diagram The block diagram in Figure 1-1 shows the structure of the MC9S08QE32 series MCU. BKGD/MS PTA7/TPM2CH2/ADP9 HCS08 CORE PTA6/TPM1CH2/ADP8 DEBUG MODULE (DBG) PTA5/IRQ/TPM1CLK/RESET PORT A PTA4/ACMP1O/BKGD/MS CPU BDC PTA3/KBI1P3/SCL/ADP3 REAL-TIME COUNTER (RTC) PTA2/KBI1P2/SDA/ADP2 HCS08 SYSTEM CONTROL SCL PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1– IIC MODULE (IIC) SDA PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ RESETS AND INTERRUPTS MODES OF OPERATION PTB7/SCL/EXTAL IRQ POWER MANAGEMENT SERIAL COMMUNICATIONS RxD1 INTERFACE MODULE(SCI1) TxD1 PTB6/SDA/XTAL COP IRQ LVD PTB5/TPM1CH1/SS RxD2 PTB4/TPM2CH1/MISO PORT B SERIAL COMMUNICATIONS TxD2 USER FLASH INTERFACE MODULE(SCI2) PTB3/KBI1P7/MOSI/ADP7 (MC9S08QE32 = 32768 BYTES) SS PTB2/KBI1P6/SPSCK/ADP6 MISO PTB1/KBI1P5/TxD1/ADP5 (MC9S08QE16 = 16384 BYTES) SERIAL PERIPHERAL MOSI INTERFACE MODULE(SPI) PTB0/KBI1P4/RxD1/ADP4 SPSCK USER RAM TPM1CLK PTC7/TxD2/ACMP2– (MC9S08QE32 = 2048 BYTES) 3-CHANNEL TIMER/PWM MODULE (TPM1) TPM1CH2–TPM1CH0 PTC6/RxD2/ACMP2+ (MC9S08QE16 = 1024 BYTES) PTC5/TPM3CH5/ACMP2O PORT C TPM2CLK PTC4/TPM3CH4 3-CHANNEL TIMER/PWM 50.33 MHz INTERNAL CLOCK MODULE (TPM2) TPM2CH2–TPM2CH0 PTC3/TPM3CH3 SOURCE (ICS) PTC2/TPM3CH2 EXTAL LOW-POWER OSCILLATOR TPM3CLK PTC1/TPM3CH1 6-CHANNEL TIMER/PWM 31.25 kHz to 38.4 kHz XTAL TPM3CH5–TPM3CH0 PTC0/TPM3CH0 1 MHz to 16 MHz MODULE (TPM3) (XOSCVLP) ACMP1O VSSA PTD7/KBI2P7 VSS ANALOG COMPARATOR ACMP1– PTD6/KBI2P6 VDDA (ACMP1) ACMP1+ VOLTAGE REGULATOR PTD5/KBI2P5 VDD PORT D ACMP2O PTD4/KBI2P4 VSSA ANALOG COMPARATOR ACMP2– PTD3/KBI2P3 VDDA (ACMP2) ACMP2+ VSSA/VREFL PTD2/KBI2P2 VDDA/VREFH PTD1/KBI2P1 10-CHANNEL, 12-BIT ADP9–ADP0 VREFL ANALOG-TO-DIGITAL PTD0/KBI2P0 VREFH CONVERTER (ADC12) PTE7/TPM3CLK KEYBOARD INTERRUPT KBI1P7–KBI1P0 PTE6 MODULE (KBI1) PTE5 PORT E PTE4 KEYBOARD INTERRUPT KBI2P7–KBI2P0 PTE3/SS MODULE (KBI2) PTE2/MISO PTE1/MOSI pins not available on 28-pin packages PTE0/TPM2CLK/SPSCK pins not available on 28-pin or 32-pin packages pins not available on 28-pin, 32-pin, or 44-pin packages Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device. When PTA4 is configured as BKGD, pin becomes bi-directional. For the 28-pin packages, VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively. The 48-pin package is the only package with the option of having the SPI pins (SS, MISO, MOSI, and SPSCK) available on PTE3-0 pins. Figure 1-1. MC9S08QE32 Series Block Diagram MC9S08QE32 MCU Series Reference Manual, Rev. 2 20 Freescale Semiconductor