Flyback Converter for Solid-State Lighting Applications with Partial Energy Processing

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The main contribution of this paper is to show a new AC/DC converter based on the rearrangement of the flyback converter. The proposed circuit only manages part of the energy and the rest is delivered directly from the source to the load. Therefore, with the new topology, the efficiency is increased, and the stress of the components is reduced. The rearrangement consist of the secondary of the flyback is placed in parallel with the load, and this arrangement is connected in series with the primary side and the rectified voltage source.

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Nội dung Text: Flyback Converter for Solid-State Lighting Applications with Partial Energy Processing

electronics Article Flyback Converter for Solid-State Lighting Applications with Partial Energy Processing Mario Ponce-Silva 1, * , Daniel Salazar-Pérez 1 , Oscar Miguel Rodríguez-Benítez 1 , Luis Gerardo Vela-Valdés 1 , Abraham Claudio-Sánchez 1 , Susana Estefany De León-Aldaco 1 , Claudia Cortés-García 1 , Yesica Imelda Saavedra-Benítez 1 , Ricardo Eliu Lozoya-Ponce 2 and Juan Antonio Aquí-Tapia 3 1 Tecnológico Nacional de México-CENIDET, Cuernavaca 62490, Mexico; daniel.salazar@cenidet.edu.mx (D.S.-P.); oscar_miguel@cenidet.edu.mx (O.M.R.-B.); luis.vv@cenidet.tecnm.mx (L.G.V.-V.); abraham.cs@cenidet.tecnm.mx (A.C.-S.); susana.da@cenidet.tecnm.mx (S.E.D.L.-A.); claudia.cg@cenidet.tecnm.mx (C.C.-G.); yesica.sb@cenidet.tecnm.mx (Y.I.S.-B.) 2 Tecnológico Nacional de México-I.T., Chihuahua 31200, Mexico; ricardo.lp@chihuahua.tecnm.mx 3 Osram Mexico, Apodaca 66626, Mexico; j.aqui@osram.com * Correspondence: mario.ps@cenidet.tecnm.mx Abstract: The main contribution of this paper is to show a new AC/DC converter based on the rearrangement of the ﬂyback converter. The proposed circuit only manages part of the energy and the rest is delivered directly from the source to the load. Therefore, with the new topology, the efﬁciency is increased, and the stress of the components is reduced. The rearrangement consist of the secondary of the ﬂyback is placed in parallel with the load, and this arrangement is connected in series with the primary side and the rectiﬁed voltage source. The re-arranged ﬂyback is only a reductive topology and with no magnetic isolation. It was studied as a power supply for LEDs. Citation: Ponce-Silva, M.; A low frequency averaged analysis (LFAA) was used to determine the behavior of the proposed Salazar-Pérez, D.; Rodríguez-Benítez, O.M.; Vela-Valdés, L.G.; Claudio- circuit and an equivalent circuit much easier to analyze was obtained. To validate the theoretical Sánchez, A.; De León-Aldaco, S.E.; analysis, a design methodology was developed for the re-arranged ﬂyback converter. The designed Cortés-García, C.; Saavedra-Benítez, circuit was implemented in a 10 W prototype. Experimental results showed that the converter has a Y.I.; Lozoya-Ponce, R.E.; Aquí-Tapia, THDi = 21.7% and a PF = 0.9686. J.A.; et al. Flyback Converter for Solid-State Lighting Applications Keywords: lighting; light-emitting diodes; LED driver; electrolytic-capacitor-less converter; partial with Partial Energy Processing. power processing converters; power factor correction (PFC) Electronics 2021, 10, 60. https://doi. org/10.3390/electronics10010060 Received: 14 December 2020 1. Introduction Accepted: 28 December 2020 Published: 31 December 2020 Nowadays, LEDs are considered the future of lighting, since they have an increasing demand caused by the long useful life that they have, around 50,000 h [1] and the lighting Publisher’s Note: MDPI stays neu- efﬁciency they present, which can reach up to 160 lm/W in the laboratory. Power supplies tral with regard to jurisdictional clai- must meet power quality standards, which contemplate total harmonic content (THDi) at ms in published maps and institutio- the input current and power factor (PF) [2]. The guidelines for lighting systems connected nal afﬁliations. to the line are speciﬁed in the IEC61000-3-2 class C standard [3]. In general, it is common to ﬁnd LED power supplies with a power factor correction (PFC) stage, after the bridge of the rectiﬁer diode, to ensure regulatory compliance. The single-stage PFC converter has the advantage of having high efﬁciency since only one Copyright: © 2020 by the authors. Li- converter processes the total energy. censee MDPI, Basel, Switzerland. However, the power supply also must convert the AC power from the main line to This article is an open access article the constant power that the LED needs for good performance [4,5], but to achieve this, distributed under the terms and con- it is necessary to have an element that can store a large amount of pulsing energy. A ditions of the Creative Commons At- large capacitor could solve this problem; however, large capacitance values are generally tribution (CC BY) license (https:// handled in electrolytic capacitors, which generate a bottleneck due to their short lifespan, creativecommons.org/licenses/by/ 4.0/). compared to LEDs, so it is recommended to avoid their use [6–8]. Electronics 2021, 10, 60. https://doi.org/10.3390/electronics10010060 https://www.mdpi.com/journal/electronics
Electronics 2021, 10, 60 2 of 16 To avoid the use of the electrolytic capacitor, another converter is usually added, in series or parallel to try to reduce the low-frequency current ripple that is supplied to the LED and operate with a low capacitance value. This solution generates a two-stage converter; the ﬁrst with the task of the PFC and the second that must compensate for the low-frequency ripple; this latter maintains the advantage of a fast control action [9,10]. This allows the use of ﬁlm capacitors that have a lifespan similar to that of LEDs [1,7,8]. However, the overall efﬁciency of the lighting system is decreased and therefore reduces the ratio lumens per watt (lm/W). This is because the total energy of the system is processed twice. Some works seek alternative solutions through other techniques, such as integrated converters [11–18], harmonic injection [19–21], ripple cancellation and ripple ports [17,22–31], and power decoupling techniques were also analyzed [32–35]. All of them have a PFC converter as the ﬁrst stage and make some adjustments in the operation of the circuit to change the energy processing and eliminate the low-frequency ripple current. In these converters, the energy is not processed twice, since they follow the principle of reduced redundant energy processing (R2 P2 ) [18,22,36–38]. They prevent the energy processed by one converter from being completely processed by another converter. Some of these jobs are called 1.5-stage converters by themselves. In this work, a converter is presented that does not seek to solve the output capacitor problem. However, the principle of reduced redundant power processing (R2P2) is taken further and created a 0.5-stage converter, which can improve the efﬁciency of any PFC converter and still comply with corresponding regulations. The proposed converter is a re-arranged variation of the ﬂyback converter; placing the secondary of the ﬂyback in parallel with the load and this arrangement is connected in series with the primary side and the rectiﬁed voltage source. This conﬁguration allows part of the energy from the source to pass directly to the load, and another part to be processed by the rearranged ﬂyback converter, thus increasing the efﬁciency of the entire system. To analyze the proposed circuit, a low frequency averaged analysis (LFAA) was carried out, which resulted in an equivalent circuit that was very easy to evaluate and thus determine its behavior and design method. As the ﬂyback converter is an isolated topology, it is possible to use some other of the aforementioned methods, such as ripple ports, to be able to eliminate low-frequency ripple current in the load. This paper is organized as follows: Section 2 presents and explains the operation and mathematical analysis of the converter. Section 3 focuses on converter design and simulation in Spice. Section 4 shows the results obtained, and ﬁnally, in Section 5, the main conclusions of this document are presented. 2. Mathematical Analysis of the Proposed Circuit The interface between the AC power supply and an LED load is called online LED driver, the driver should have a power factor greater than 0.9 according to the U.S. Energy Star program [2]. The LED drivers must also comply with the current harmonics level speciﬁed in IEC 61000-3-2 Class C [3]. Therefore, a Power Factor Converter (PFC) should be used to meet the usual requirements for an LED power supply. In Figure 1 the proposed topology is shown. The converter consists of a variation of the ﬂyback converter in which the secondary stage is connected in parallel with the LED lamp and these in turn in series with the primary stage.
Electronics 2021, 10, x FOR PEER REVIEW 3 of 18 iac LED1 v Electronics 2021, 10, x FOR PEER REVIEW ac Lp 3 of 18 Electronics 2021, 10, 60 3 of 16 iac . Convertidor LED1 n LED vac Lp FlyBack . . iac Convertidor Ls LEDn FlyBack LED1 vac Lp Ls . Figure 1. Proposed topology: Rearranged flyback converter, with primary and secondary in series. . Convertidor LEDn In order to carry out the analysis of the rearranged flyback converter, a low-frequency FlyBack Figure 1. Proposed topology: Rearranged flyback converter, know in a general way if a topology average analysis (LFAA) was used; This is used to with primary and secondary in series. Ls . complies with the corresponding regulations, knowing its efficiency, and evaluating its feasibility of implementation. The LFAArearranged flyback converter, a low-frequency at In order to carry out the analysis of the model the behavior of the flyback converter average analysis (LFAA) was used; This isdue to to know in a general way if mode (DCM) the frequency line. At this frequency and used the discontinues conduction a topology complies Proposed topology:the primaryflyback converter, with efficiency, and evaluating itsF), Figure 1. with the corresponding regulations, converter, withprimaryloss-free resistance (R of the flyback converter, Rearranged side canknowing its Figure 1. Proposed topology: Rearranged ﬂyback be represented as a and secondary in series. primary and secondary in series. this resistance represents the average power delivered to the primary side of the flyback feasibility of implementation. The LFAA model the behavior of the flyback converter at the frequency line. Atenergy “consumed” theto the discontinuesconverter, a amode (DCM) converter (Pto carrythis frequency and the rearranged flybacktransferred to low-frequency In order Fito the out the analysis of due this resistance is conductionlow-frequency In order ), carry out the analysis of by rearranged ﬂyback converter, the secondary ofaveragethe flyback converterused; isThis isused toaknow inasaageneralway source (VF), as average analysis (LFAA) primary modeled as know sideflyback converter, thewas that side can used to direct current voltage ififaatopology the of analysis (LFAA) was used;This is be representedina general way loss-free resistance (RF), topology complies with the2. corresponding regulations, knowingthe primary and evaluating its shown in Figure this resistance represents the average power delivered to its efficiency,side ofevaluatingits complies with thecorresponding regulations, knowing its efﬁciency, and the flyback converter (PFi), implementation. The LFAAas a series direct DCof the flyback converter at feasibilitythe implementation.be modeled model the behavior voltage source converter at feasibility ofLED energy can The LFAA this resistance is transferred to the secondary On of the side, it “consumed” by model the behavior of the ﬂyback with a resis- theof the flybackFigure 3. frequency and due as the discontinues conduction mode (DCM) tor, frequency line. At this that is and due to a discontinues conduction mode (DCM) as shown in converter side frequency line. At this frequency modeledto the direct current voltage source (VF), as the shown Figure 4converter, the primary side can be represented as aaloss-free resistancecircuit of the flyback converter, the primary low-frequency scheme corresponding to the (RF),), of thein Figureshows the equivalent side can be represented as loss-free resistance (RF ﬂyback 2. this resistance represents the vr is the as a delivered to the primary side of the resis- this resistance represents the modeledrectified Voltage, tois the rectified Current, flyback proposed in Figure 1. Where: average power delivered iDC voltage sourceof the aVF is the On the LED side, it can beaverage powerseries direct r the primary side with ﬂyback tor, as shownFiin), the the secondary of the by this resistance isRF Loss-free tothe secondary converter voltage in energy “consumed” flyback converter, transferred to the secondary converter (PFi the energy “consumed” by this resistance is transferred resistance repre- average (P ), Figure 3. sideFigure flyback the equivalent ismodeled V representing thevoltage source circuitas sideof the 4ﬂybackconverter that isconverter, asDaaschemecurrent voltage source (VFF ),as sentingthe primary of the flyback low-frequency direct current LED threshold (V ), of the shows converter that modeled as direct corresponding to the voltage proposedin Figure2. 1. Where: vr is the rectified Voltage, ir is the rectified Current, VF is the shownLEDFigure2. RD is the resistance of the LED model. of the inin model, shown Figure average voltage in the secondary of the flyback converter,DC voltage source with a resis- On the LED side, it can be modeled as a series direct RF Loss-free resistance repre- Primary Secondary senting shown in Figure 3. flyback converter, VD representing the LED threshold voltage tor, as the primary of the of theFigure 4 shows is the resistancelow-frequency scheme corresponding to the circuit LED model, RD the equivalent of the LED model. Primary . proposed in Figure 1. Where: vr is the rectified Voltage, ir is the rectified Current, VF is the Secondary average voltage in the secondary of the flyback converter, RF Loss-free resistance repre- VCD RF senting the primary of the flyback converter, VD representing the LED threshold voltage . . of the LED model, RD is the resistance of the LED model. VCD RF Primary Secondary . . Figure 2. Flyback model in DCM for the LFAA. Figure 2. Flyback model in DCM for the LFAA. RF On the LED side, it can be modeled as a VCD direct DC voltage source with a resistor, series as shownVin Figure 3. . Figure 2. Flyback model in DCM for the LFAA. D VD RD Figure 2. Flyback model in DCM for the LFAA. Figure 3. D R LED model. VD Figure 3. 3. LED model. Figure LED model. RD Figure 4 shows the equivalent low-frequency scheme corresponding to the circuit proposed in Figure 1. Where: vr is the rectiﬁed Voltage, ir is the rectiﬁed Current, VF is the average voltage in the secondary of the ﬂyback converter, RF Loss-free resistance Figure 3. LED model. representing the primary of the ﬂyback converter, VD representing the LED threshold voltage of the LED model, RD is the resistance of the LED model.
Electronics 2021, 10, x FOR PEER REVIEW 5 of 18 Electronics 2021, 10, x FOR PEER REVIEW Electronics 2021, 10, 60 4 ofof 16 4 18 50 iac  a0    an cos  nt   bn sin  nt   n 1 (7) dc ac Therwaveform beingDanalyzed (iac) is an odd function, therefore there are only odd i i + harmonics. The THDi is obtained from (8), where I1 is the fundamental component that is Flyback Model defined in (9), and In + V is the amplitude of the n-th harmonic that is defined in (10). F VD LED vr Lamp vLED iF 2 Model 50 I  - RD THDi  100    In  n 3  1  (8) vRF - + - RF   I1  2cos t x sin t x  4m  Figure 4. 4. Equivalent circuit for low-frequency analysis. cos Figure Equivalent circuit for low-frequency analysis.  tx   2t x   (9) The loss free resistance evaluated with the following expression:   The loss free resistance isis evaluated with the following expression:   m  n 2  1 cos nt     x   PFi 2  PFi Fi PFi P  4 R F F  22n   n 2 T n  R=  = T (1) In  sinIRrms    2 22 i2 dtsin   n  1 t x    IRrms 2 2  (1) n  n  1 n  1  2   0 0i2dt  (10) T r r  T 2   n  n   sin   n  1 t x   where IRrms is the RMS value of i . where IRrms is the RMS value of ir. r  2    2.1. Analysis of the Power Factor (PF) and the Current Total Harmonic Distortion (THDi) Using  2.1. Analysis of the Power Factor (PF) and the Current Total Harmonic Distortion (THDi) LAAA Returning to (8) and assuming the main voltage is sinusoidal the PF is obtained by: Using LAAA In Figure 4, it is observed that the LED is powered by the voltage source VF , it is 1 interesting to4, it is observed that the ir . is powered by the voltage source VF, it is In Figure obtain the expression of LED PF applying Kirchhoff’s voltage law to the scheme interesting to obtain the expression of ir. applying Kirchhoff’s voltage law to the scheme we obtain: THDi 2 (11) we obtain: v LED = VF = D 100  1V + i 2 · R (2) D D vLED  VF  r −  FD  RD ir = v VD Vi (2)m Figure 6 shows the plot of (8), assuming THDi ≤ 32%., it can be seen that the gain(3) RF can vary from 0 to 0.46. If m > 0.46 the THDi  V be very high and the power factor PF v will ir  r F Additionally, the following observations were made: very low. (3) RF 1. Regarding the requirementsso it is IEC61000-3-2, Figure < Vr , where Vr is the peak The topology is reductive, of the always true that VF 7 shows the curves for the voltage of v the n shown = (4). odd harmonics from following in 15, it is observedmade: topology is limited in a range Additionally, r (t), as= 3 to n observations were that the 2. < There will be current ﬂow through RF if vr > VF , when vr < VF the current i (t) = 0, as 1.of 0The topology is reductive, so it is always true that VF < Vr, where Vr is the peakr voltage m < 0.41. From as shownVF there willis plotted, it can be times.that the topologywaveform will Vr approaches where (11) be very long death seen Therefore, the ir meets the re- of vr(t), Figure 8, in (4). be the same as i90at T/2 as shown in Figure 5. 2.quirements of bePF > ac without a problem in > VF, when 0 r
Electronics 2021, 10, 60 5 of 16 where m = VF /Vr is the gain of the proposed converter, ω is the angular frequency and f is the line frequency. In order to calculate the PF and THDi in the proposed converter, it is necessary to know the harmonics of the input current waveform (iac ), shown in (6). For this, tx can be used in the integration limits of the calculation of the Fourier coefﬁcients of iac in (7) and verify if the topology meets the requirements of IEC61000-3-2 class C. Vr sin(ωt)−VF T RF tx 0.46 the THDi will be very high and the power factor PF very low. THDi m Figure 6. THDi of topology vs gain (m). Regarding the requirements of the IEC61000-3-2, Figure 7 shows the curves for the odd harmonics from n = 3 to n = 15, it is observed that the topology is limited in a range of 0 < m < 0.41.
THDi Electronics 2021, 10, 60 6 of 16 m Figure 6. THDi of topology vs gain (m). m Figure 6. THDi of topology vs gain (m). n=3 % n=3 % n=5 n=7 n=5 n=9 n=11 n=7 m n=9 n=11 Figure 7. 7. Curves of each harmonic of the topology vs the gain (m). Figure Curves of each harmonic of the topology vs the gain (m). m From Figure 8, where (11) is plotted, it can be seen that the topology meets the requirements of a PF > 90 without a problem in a range of 0 < m < 0.41. Figure 7. Curves of each harmonic of the topology vs the gain (m). PF PF m Figure 8. PF of the topology vs the gain (m). m Figure 8. PF of the topology vs the gain (m). Figure 8. PF of the topology vs the gain (m). From this section it is concluded that the proposed topology complies with all applica- ble standards in the range of 0 < m < 0.41. 2.2. Analysis of the Power Flow in the Converter In order to analyze the power ﬂow in the proposed converter the following concepts are deﬁned in Table 1. Figure 9 shows the power ﬂow diagram of a conventional ﬂyback compared with the proposed rearranged ﬂyback. In this diagram, it is easier to understand the operation of the proposed converter, in which it is observed as part of the input power Pi is supplied directly to the load, while the other fraction is processed by the PFi ﬂyback converter. Therefore, the total efﬁciency concerning the conventional ﬂyback will be improved.
Average power delivered to the primary side of 1 T (14) T 0 PFi PFi  vRF ir dt the flyback converter Average power delivered by the secondary side 1 T (15) T 0 PFo PFo  VF ir dt of the flyback converter Electronics 2021, 10, 60 Ratio between the power processed by the fly- 7 of 16 P (16) Q back converter and the input power of the pro- Q  Fi Pi posed converter Table 1. Power ﬂow concepts. the proposed converter  PL (17) η Efficiency of Pi Symbol Description P Deﬁnition (18) ηF Efficiency of the flyback F  Fo PL Average power consumed by the load 1 PT PL = T Fi v LED id dt (12) 0 Pi Average power delivered by the main source 1 T Pi = T 0 vr ir dt (13) Figure 9 shows the power flow diagram of a conventional flyback compared with the Average power delivered to the primary side of the 1 T PFi PFi = T 0 v proposed rearranged flyback. ﬂyback converter it is easier to understand the RF ir dt (14) In this diagram, operation of the proposed Average powerwhich it is observed as part of the input power Pi isdt (15) PFo converter, in delivered by the secondary side of the P = T 0 VF i supplied 1 T ﬂyback converter is processed by theFo Fi flyback rconverter. directly to the load, while the other fraction P Ratio between the power processed by the ﬂyback Therefore, the total efficiency concerning the conventional flyback willPFi improved. be Q converter and the input power of the proposed Q = Pi (16) The percentage of power processed by the flyback is called the constant Q. The range converter of Q must be 0 < Q < 1,Efﬁciency of the than 1 there is no point in implementing the topology η if Q is greater proposed converter η = PL (17) Pi since η instead of having benefits, low efficiency and greater electrical size would be ob- Efﬁciency of the ﬂyback η F = PFo (18) F PFi tained concerning an isolated basic flyback. (a) Pi=PFi FlyBack PFo=ɳF*PFi PL=PFo PL ɳF Pi Pi-PFi=Pi-Q*Pi=Pi(1-Q) PL=PFo+Pi(1-Q) (b) PL=Pi(Q(ɳF-1)+1) FlyBack PFi=Q*Pi PL ɳF PFo=ɳF*Q*Pi Figure 9. Power ﬂow diagrams, (a) conventional ﬂyback and (b) proposed rearranged ﬂyback. Pi is Figure 9. Power flow diagrams, (a) conventional flyback and (b) proposed rearranged flyback. Pi is the input power to the converter. the input power to the converter. The percentage of power processed by the ﬂyback is called the constant Q. The range According to Figure 9 the total efficiency η of the converter will be: of Q must be 0 < Q < 1, if Q is greater than 1 there is no point in implementing the topology since instead of having beneﬁts, low efﬁciency and greater electrical size would be obtained PL concerning an isolated basic ﬂyback.  Q  F  1  1 (19) Pi According to Figure 9 the total efﬁciency η of the converter will be: This equation was plotted in Figure 10 assuming an arbitrary value for the flyback P efficiency ηF = 0.9. As can be seen η = Lfigure,ηregardless of the Q value, the efficiency of in this = Q( F − 1) + 1 (19) Electronics 2021, 10, x FOR PEER REVIEW Pi 8 of 18 This equation was plotted in Figure 10 assuming an arbitrary value for the ﬂyback efﬁciency η F = 0.9. As can be seen in this ﬁgure, regardless of the Q value, the efﬁciency of the proposed converter will always bebe greater than the efficiencyaof a conventional fly- the proposed converter will always greater than the efﬁciency of conventional ﬂyback. Total efﬁciency will increase as the ﬂyback converter processes less energy.energy. back. Total efficiency will increase as the flyback converter processes less 1 0.98 0.96 ɳ Efficiency 0.94 0.92 ɳF 0.9 0.88 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Q Figure 10. Estimated efﬁciency of the proposed converter vs Q. Figure 10. efficiency of the proposed converter vs Q. Substituting (3) and (4) in the expressions of Table 1 with the definition of m: VF T t PFo   2 x ir dt T tx 2 (20) mVr2  2 mt x   m  2cos t x   
Electronics 2021, 10, 60 8 of 16 Substituting (3) and (4) in the expressions of Table 1 with the deﬁnition of m: VF T/2−t x PFo = T tx ir dt 2 2 (2ωmt − πm +2 cos( ωt )) (20) mVr x x = RF π RF T/2−t x 2 PFi = T tx ir dt 2 2 2 cos( ωt )[sin( ωt )−4m cos( ωt )]+( π −2ωt ) 1+2m2 Vr ( (21) x x x x ( )) = RF π 1 T/2−t x Pi = T tx vr ir dt 2 2 (2 cos( ωt ) sin( ωt )−4m cos( ωt )−2ωt + π ) (22) Vr x x x x = RF π −2ωm2 t x + πm2 − 2m cos(ωt x ) Q= +1 (23) cos(ωt x ) sin(ωt x ) − 2m cos(ωt x ) − ωt x + π/2 1 T/2−t x Iravg = Ttx ir dt 2 Vr (2ωmt x −πm+2 cos(ωt x )) (24) = RF π In Figure 11, the graph (23) is obtained, in which it is observed that when m increases, Q Electronics 2021, 10, x FOR PEER REVIEW decreases; this is favorable since the ﬂyback by processing fewer power beneﬁts the total 9 of 18 efﬁciency of the system. Q m Figure 11. Percentage of of power processed by the ﬂyback Q vs Gain m. Figure 11. Percentage power processed by the flyback Q vs Gain m. 3. 3. Design of the Rearranged Flyback Design of the Rearranged Flyback For the implementation ofof the rearranged ﬂyback converter circuit, LEDs were pur- For the implementation the rearranged flyback converter circuit, LEDs were pur- chased from the manufacturer Seoul Semiconductor with part number SAW0LH0A. An chased from the manufacturer Seoul Semiconductor with part number SAW0LH0A. An array ofof LEDs was made inin parallel, which is shown in Figure 14. array 8 8 LEDs was made parallel, which is shown in Figure 14. The resulting specifications ofof the LED array are shown in Table 2, which will be used The resulting speciﬁcations the LED array are shown in Table 2, which will be used to simulate at low frequency. to simulate at low frequency. Table 2.2. Technical speciﬁcations of the LED test lamp. Table Technical specifications of the LED test lamp. VD VD RRD D ID ID VLED VLED PL L P 56 V V 56 28.1 ΩΩ 28.1 160 mA mA 160 60.5 V60.5 V 9.68 WW 9.68 InIn order to calculate the components of the converter, some design parameters must order to calculate the components of the converter, some design parameters must be proposed, which are shown inin Table 3, among them it is worth noting that the ﬂyback be proposed, which are shown Table 3, among them it is worth noting that the flyback dead time is is deﬁned in DCM for AC-DC converters [16]. With the values of Table 3, and dead time defined in DCM for AC-DC converters [16]. With the values of Table 3, and the equations previously developed, the necessary values for the implementation of the converter are shown in Table 4. Table 3. Design parameters proposed. Parameter Equation and Value
Electronics 2021, 10, 60 9 of 16 the equations previously developed, the necessary values for the implementation of the converter are shown in Table 4. Electronics 2021, 10, x FOR PEER REVIEW 10 of 18 Table 3. Design parameters proposed. Parameter Equation and Value Table 4. Design ofLine proposed converter. the voltage v ac = 127 Vrms √ Peak voltage Vr = 127 · 2 ≈ 180 V Parameter Proposed ﬂyback efﬁciency Equation and Value η F = 0.95 Average tensionin the secondary VF 60.5VV = 60.5 V VLED =  0.336 Gain m  F Proposed duty cycle Vr 180V 0.405 D= Switching frequency sin 1  m  = 107 kHz fs Dead time of ir. tx   909.26 s Proposed duty cycle of discharge  Desc = 0.302 Proposed voltage ripple THDi  22.56% THDi %VRip = 16% EMI capacitor used PF Cemi ≈ 92 nF PF  97.55% Primary winding impedance RF  971.918 , Table 4. Primary winding power Design of the proposed converter. PFi  5.904W , Average input current iravg  62.41mA Parameter Equation and Value PFi Electrical Size Q  V  60.9% Gain m = Pi F = 60.5V Vr 180V ≈ 0.336 Average flyback time of irpower Dead output . PFo  sinPi1 ( 5.6W tx = F − m) = 909.26 µs ω Average voltageTHDi primary at the Vin  PFi .RF i  75.6V THD = 22.56% PF PF = 97.55% PFo Primary winding impedance Average current in the secondary I o  R F= 971.918 Ω, 92.65mA VF Primary winding power PFi = 5.904 W, Vo  Vdiode 60.5  1 mA iravg = 62.410.813 Flyback convertercurrent Average input gain M   Vin Q = PFi = 60.9% 75.7 Electrical Size Pi Discontinuity parameter Average ﬂyback output power k  PFo = ηF Pi ≈ 5.6 W Desc  0.248 √ Average voltage at the primary Vin = VinPFi .R F ≈ 75.6 V D2 * 2 Primary inductance Lp   757uH Average current in the secondary Io = PFo 2* PFi *Vf s ≈ 92.65 mA F Vo +Vdiode Flyback converter gain M= D = 60.5+1 ≈ 0.813 Transformation relation N √  1.659 Vin 75.7 Discontinuity parameter k = Desc ≈ 0.248 M * Desc D2 ∗Vin 2 Primary inductance Secondary inductance L L p  278.4uH Ls  p = 2∗ PFi ∗ f s ≈ 757 uH Transformation relation N2 N = M∗D ≈ 1.659 P L Desc Secondary inductance Capacitor C = N 2 V  22 uH i Ls Hz Vp2 ≈ 278.4uF 4    60 F rip P Capacitor C = 4·π ·60Hzi ·V 2 ·V ≈ 22 uF 1 Lemi  1 2  2.7 mH F rip Calculated EMI inductor Calculated EMI inductor Lemi ≈ f  f 2 ≈ 2.7 mH C  10  10 Cemi   2 emi · 2·π ·   In order to evaluate the proposed circuit before the implementation, a simulation of In order to evaluate the proposed circuit before the implementation, a simulation of the circuit was made in Spice. In Figure 12, The schematic is shown, and the results of the the circuit was made in Spice. In Figure 12, The schematic is shown, and the results of the simulation are shown in Figure 13. simulation are shown in Figure 13. 2.7m L3 R3 V4 C3 VOFF = 0 PARAMETERS: VAMPL = 180 92n C = 22u FREQ = 60 0.001 D = .405 AC = 0 0 f s = 107k C2 R1 L1 = 757u {C} {Rd} L2 = 278.4u L2 Rd = 28.1 K K2 {L2} IC = 60 Vd = 56 Q1 V3 K_Linear R2 n = {sqrt(L1/L2)} V1 = 0 V1 COUPLING = 1 Q1 0.001 {Vd} Ts = {1/f s} V2 = 5 L1 = L1 TD = 0 TR = 10n L2 = L2 TF = 10n 0 + - PW = {D/f s} S1 {L1} + PER = {1/f s} - S 0 L1 Figure 12. Proposed circuit simulated in spice. Figure 12. Proposed circuit simulated in spice.
Electronics 2021, 10, 60 FOR PEER REVIEW Electronics 2021, 10, x 10 of 16 11 of 18 80V 60V 40V vo 400mA Electronics 2021, 10, x FOR PEER REVIEW 11 of 18 200mA 0A io 750mA 500mA 80V iL1 60V 0A 200mA 40V vo 400mA 0A iin 200mA -200mA 67 0A ms 70 ms 75 ms io 80 ms Time 85 ms 90 ms 95 ms 100 ms 750mA 500mA i Figure 13. Waveforms resulting from the simulation in Spice. Output voltage (vo ), output current (ioo),current of the primary Figure 13. Waveforms resulting from the simulation in Spice. Output voltage (vo), output current (i ), current of the primary side (iL1 ), and input current (iin). L1 side (iL1), and input current (iin ). 0A 200mA 0A i 4. Experimental Results 4. Experimental Results in -200mA A laboratory prototype has been built to carry out experimental tests and evaluate laboratory prototype has been built to carry out experimental tests and evaluate A 75 67 70 80 85 90 95 100 ms ms the performance of themsproposedconverter. an IR2106 driver and a MOSFETms the performance of theproposed converter. an IR2106 driver and a MOSFETIRF840 were ms Time ms ms ms IRF840 were used. The prototype for experimental tests is shown in Figure 14. used. The prototype for experimental tests is shown in Figure 14. Figure 13. Waveforms resulting from the 15 shows the main line current and voltage waveforms. AsAs the primary this Figure 15 shows the main line current (vo), output current (io), currentcan be seen in in Figure simulation in Spice. Output voltage and voltage waveforms. of can be seen side (iL1), and input currentthis Figure the current waveform shows the death tx predicted by the LFAA and this wave- Figure the current waveform shows the death time time tx predicted by the LFAA and this (iin). form is similar to the theoretical waveform shown in Figure 5. waveform is similar to the theoretical waveform shown in Figure 5. The THDi of the input waveforms of Figure 15 was measured with the HIOKI model The THDi of the input 4. Experimental Results waveforms of Figure 15 was measured with the HIOKI model PW3198laboratory prototype haswhich built to carry out experimental teststhatthe THDi PW3198 power quality analyzer, whichis shown in Figure 16, which shows that the THDi A power quality analyzer, been is shown in Figure 16, which shows and evaluate is close to 21.7% andthe proposed converter. anthe requirements ofa theEN 61000-3-2 class is close to 21.7% and the harmonics are within the requirements ofthe EN 61000-3-2 class the performance of the harmonics are within IR2106 driver and MOSFET IRF840 were C standard. As for the PF obtained intests is shown in with the energy quality meter, it C standard. As for the PF obtained in experimental testsFigure 14.energy quality meter, it is used. The prototype for experimental experimental tests with the shown to to 15 shows in Figure line is shown be be 0.9686 Figure 17.17. current and voltage waveforms. As can be seen in this Figure 0.9686 in the main Figure the current waveform shows the death time tx predicted by the LFAAtests this wave- The instantaneous voltage of the LED lamp obtained in experimental and is shown form is similar to average voltage applied to the LED was V in Figure 18. The the theoretical waveform shown in Figure 5. LED = 60.5, the same of the speciﬁcations, the the input waveforms of Figure 15 wasThe instantaneous current of the The THDi of voltage ripple obtained was 18.16%. measured with the HIOKI model LED lamp obtained in analyzer, which is shown in Figure 16, which shows that the THDi PW3198 power quality experimental tests is shown in Figure 19. The average current applied to the LED was ILED = 160.3 mA,within the requirements of the EN 61000-3-2 class is close to 21.7% and the harmonics are the current ripple obtained was 212%. Finally, in Figure 20 theAs for the PF obtained power in the LED is shown. which shows an average C standard. instantaneous output in experimental tests with the energy quality meter, it power of Po = 10.62 W.in Figure 17. is shown to be 0.9686 Figure 14. Prototype of the topology for experimental tests. The instantaneous voltage of the LED lamp obtained in experimental tests is shown in Figure 18. The average voltage applied to the LED was VLED = 60.5, the same of the spec- ifications, the voltage ripple obtained was 18.16%. The instantaneous current of the LED lamp obtained in experimental tests is shown in Figure 19. The average current applied to the LED was ILED = 160.3 mA, the current ripple obtained was 212%. Finally, in Figure 20 the instantaneous outputtopologyin the LED is shown. which shows an average power of Figure 14. Prototype of the power for experimental tests. Figure 14. Prototype of the topology for experimental tests. Po = 10.62 W. Finally, Tables 5 and 6 summarize what was obtained in the implementationshown The instantaneous voltage of the LED lamp obtained in experimental tests is of the topology 18. The average voltage applied to the LED was VLED = 60.5,there are parameters in Figure and the percentages of error obtained, and as expected, the same of the spec- ifications, the voltage ripple obtained was 18.16%. The instantaneous current of the LED lamp obtained in experimental tests is shown in Figure 19. The average current applied to the LED was ILED = 160.3 mA, the current ripple obtained was 212%. Finally, in Figure 20 the instantaneous output power in the LED is shown. which shows an average power of
such as in the case of THDi with a higher percentage of error, this is since losses of the such as in the case of THDi with a higher percentage of error, this is since losses of the elements used were not considered, in addition to this the construction of the prototype, elements used were not considered, in addition to this the construction of the prototype, Electronics 2021, 10, 60 to mention the manual manufacture of the transformer, which can considerably affect the 11 of 16 to mention the manual manufacture of the transformer, which can considerably affect the performance of the entire system. performance of the entire system. It should be noted that the flyback only processes 63% of the input power. It should be noted that the flyback only processes 63% of the input power. vac vac iac iac Figure 15. Main line current iiiac (200 mA/div) and voltage vvac(60 V/div). Figure 15. Main line current ac (200 mA/div) and voltage ac (60 V/div). Figure 15. Main line current ac (200 mA/div) and voltage vac (60 V/div). Electronics 2021, 10, x FOR PEER REVIEW 13 of 18 Figure 16. THDi obtained in experimental tests of the power quality meter. Figure 16. THDi obtained in experimental tests of the power quality meter. Figure 16. THDi obtained in experimental tests of the power quality meter. Figure 17. PF obtained in experimental tests of the power quality meter. Figure 17. PF obtained in experimental tests of the power quality meter.
Electronics 2021, 10, 60 12 of 16 Figure 17. PF obtained in experimental tests of the power quality meter. Ripple voltage = 18.16% Electronics 2021, 10, x FOR PEER REVIEW 14 of 18 Figure 18. Instantaneous voltage in experimental tests of the LED lamp. 10 V/div, average voltage Figure 18. Instantaneous voltage in experimental tests of the LED lamp. 10 V/div, average voltage in the LED 60.5 V. in the LED 60.5 V. Ripple current = 212% Figure 19. Instantaneous current in experimental tests ofof the LED lamp. 100 mA/div, average cur- Figure 19. Instantaneous current in experimental tests the LED lamp. 100 mA/div, average current in the LED LED 160.3 mA. rent in the 160.3 mA.
Electronics 2021, 10, 60 13 of 16 Figure 19. Instantaneous current in experimental tests of the LED lamp. 100 mA/div, average cur- rent in the LED 160.3 mA. Figure 20. Instantaneous power in experimental tests of the LED lamp. 3 W/div, average power in Figure 20. Instantaneous power in experimental tests of the LED lamp. 3 W/div, average power in the LED 10.62 W. the LED 10.62 W. Finally, Tables 5 and 6 summarize what was obtained in the implementation of the topology and the percentages of error obtained, and as expected, there are parameters such as in the case of THDi with a higher percentage of error, this is since losses of the elements used were not considered, in addition to this the construction of the prototype, to mention the manual manufacture of the transformer, which can considerably affect the performance of the entire system. It should be noted that the ﬂyback only processes 63% of the input power. Finally, Table 7 shows a small comparison with a couple of similar power topologies. It can be seen that the topology has a good efﬁciency and power factor compared to the other two topologies, and even less energy stored in the capacitor is reported, which translates into a physically smaller capacitor. However, it has a greater current ripple. Table 5. Summary of results of the topology. Parameter Ideal PSpice Prototype THDi 22.58% 19% 21.7% PF 97.55% 97.9% 96.86% Average lamp voltage VLam 60.5 V 60.56 V 60.5 V Voltage ripple percentage 16% 14.86% 18.16% Average lamp current ILam 160 mA 159 mA 163 mA Current ripple percentage 0 194.8% 212.1% Average lamp power PLam 9.68 W 9.62 W 10.61 W Average rectiﬁed power Pi 9.68 W 10.4 W 11.55 W Processed power Q 60.96% 61.5% 62.94% Flyback efﬁciency η F 95% 90% 88% Efﬁciency w/o bridge rectiﬁer η T 95% 92.5% 91.4% Efﬁciency AC line-lamp η S 95% 90.8% 88.79%
Electronics 2021, 10, 60 14 of 16 Table 6. Error rates in the topology. % Error Ideal-Spice Ideal-Prototype Spice-Prototype THDi −15.85 −3.89 14.21 PF 0.358 −1.014 −1.36 Average lamp voltage VLam 0.099 0 −0.099 Voltage ripple percentage −7.25 13.3 22.2 Average lamp current ILam −0.625 0.18175 0.8176 Current ripple percentage - - 8.88% Average lamp power PLam −0.6198 9.607 10.29 Average rectiﬁed power Pi 7.43 19.3 11.05 Processed power Q 0.885 3.24 2.34 Flyback efﬁciency η F −5 −7.36 −2.2 Efﬁciency w/o bridge rectiﬁer η T −2.63 −3.78 −1.189 Efﬁciency AC line-lamp η S −4.42 −6.53 −2.21 Table 7. Comparison with other reported topologies. Potencia de Current Output Energy in the Topology THDi PF Efﬁciency Capacitor Lámpara Ripple Voltage Capacitor [15] 20 W - 80.3% 80% 14.6% 10 uF 390 V 760 mJ [13] 9.8 W 17% 97% 87% 14.1% 4.7 uF 243 V 138 mJ This paper 10.61 W 21.7% 96.56 88.79% 212.1% 22 uF 66 V 47.9 mJ 5. Conclusions Through this document, a new converter has been evaluated which is based on a variant of the ﬂyback converter and is used as a power supply in solid-state lighting systems. The proposed converter consists of a rearrangement of the components of the conven- tional ﬂyback, the secondary is placed in parallel with the LED load and this set is in turn placed in series with the primary and the voltage source. The primary advantage of this converter is the partial processing of energy, which goes beyond the principle of reduced redundant energy processing (R2 P2 ) [16], one part of the energy is directly delivered to the load and the other part is processed by the converter. Since in this rearrangement the ﬂyback converter processed less energy, the stress in the components is lower than in a conventional ﬂyback. As well, this operation allows the efﬁciency of the proposed converter to always will be greater than the conventional ﬂyback converter. The main disadvantages are the converter have not magnetic isolation, it is a reductive topology and the power factor depends on the gain m of the converter. The mathematical analysis of the topology of the retroﬁtted ﬂyback converter was performed and it was shown that it complies with the requirements established by the IEC61000-3-2 class C standard and the FIDE directives in an interval of 0 < m < 0.41, with a THDi = 21.7% and a PF = 0.9686. In order to validate the mathematical calculations, a 10 W prototype was built. Experi- mental results show the rearranged ﬂyback processed only 63% of the input power and the other 37% ﬂows directly to the load. Author Contributions: Conceptualization, D.S.-P., M.P.-S. and J.A.A.-T.; data curation, D.S.-P., M.P.-S. and O.M.R.-B.; formal analysis, D.S.-P., M.P.-S., A.C.-S. and L.G.V.-V.; funding acquisition, M.P.-S., R.E.L.-P., Y.I.S.-B. and C.C.-G.; investigation, D.S.-P., M.P.-S. and S.E.D.L.-A.; methodology, M.P.-S., L.G.V.-V. and C.C.-G.; project administration, R.E.L.-P., Y.I.S.-B.; resources, O.M.R.-B., M.P.-S., A.C.-S. and L.G.V.-V.; software, Y.I.S.-B., A.C.-S. and C.C.-G.; supervision, M.P.-S. and J.A.A.-T.; validation, D.S.-P., M.P.-S. and O.M.R.-B.; visualization, D.S.-P., M.P.-S., A.C.-S. and L.G.V.-V.; writing—original
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