Master's thesis of Engineering (Research): FPGA implementation of short word-length algorithms

The design proposed in this thesis aims to reduce the distortion in Class-D Amplifier output at the cost of increased complexity in the implementation. The thesis is focussed on the DSP components of the unique design. State-ofthe-art FPGAs have been used as the implementation platform for these systems due to advantages such as abundant logic resources, ease of programming and re-configurability. The results demonstrate advantages of SWL processing systems in terms of efficient hardware utilization. I hope that this work will help researchers in the fields of audio amplifiers and SWL systems and inspire further research in these fields.