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The design proposed in this thesis aims to reduce the distortion in Class-D Amplifier output at the cost of increased complexity in the implementation. The thesis is focussed on the DSP components of the unique design. State-ofthe-art FPGAs have been used as the implementation platform for these systems due to advantages such as abundant logic resources, ease of programming and re-configurability. The results demonstrate advantages of SWL processing systems in terms of efficient hardware utilization.

130p runthenight07 01-03-2023 7 3   Download