CMOS combinational logic circuits

Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model.

6p kequaidan1 16-11-2019 25 0   Download

(bq) part 2 book "digital integrated circuits prentice hall" has contents: designing combinational logic gates in cmos, designing sequential logic circuits, coping with interconnect, timing issues in digital circuits.

249p bautroibinhyen21 14-03-2017 72 3   Download