Verilog keywords

This paper describes a compiler, which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics, of Verilog and performs logic minimization. Busses of up to 32 or 64 bits can be modeled as C integers whereas larger busses are automatically split. We describe the motivation, method and quality of the results.

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Certified that the work contained in the thesis entiled " Verilog-to-C-Compiler: Simulator Generator " by " Anand Vivek Srivastava", has been carried out under my supervision and that this work has not been submitted elsewhere for a degree. This paper describes a compiler, which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics, of Verilog and performs logic minimization.

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Sequential and Parallel Blocks Block statements are used to group multiple statements to act together as one. In previous examples, we used keywords begin and end to group multiple statements.

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Functions Functions are declared with the keywords function and endfunction. Functions are used if all of the following conditions are true for the procedure

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[ Team LiB ] 3.1 Lexical Conventions The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. Verilog contains a stream of tokens. Tokens can be comments, delimiters, numbers, strings, identifiers, and keywords.

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