Implementation and validation of memory built in self test (MBIST) - survey

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This paper provides a survey of Implementation and Validation involved in Memory Built in Self-Test (MBIST). This paper comprises of the various strategies involved in the implementation and Validation of the Memory Built in Self-Test (MBIST).

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International Journal of Mechanical Engineering and Technology (IJMET) Volume 10, Issue 03, March 2019, pp. 153-160. Article ID: IJMET_10_03_015 Available online at http://www.iaeme.com/ijmet/issues.asp?JType=IJMET&VType=10&IType=3 ISSN Print: 0976-6340 and ISSN Online: 0976-6359 © IAEME Publication Scopus Indexed IMPLEMENTATION AND VALIDATION OF MEMORY BUILT IN SELF TEST (MBIST) - SURVEY A.M Aswin Second year M.Tech, Department of Embedded System Technology, SENSE S.Sankar Ganesh Assistant Professor Senior, Department of Communication Engineering, SENSE Vellore Institute of Technology, Vellore-632014, Tamil Nadu, India ABSTRACT This paper provides a survey of Implementation and Validation involved in Memory Built in Self-Test (MBIST). This paper comprises of the various strategies involved in the implementation and Validation of the Memory Built in Self-Test (MBIST). MBIST (Memory built-in self-test) provides an effective solution for testing of such large memories. Verification of functioning MBIST is an essential part in any SoC design cycle, as it enables the designer to detect beforehand any issues related to MBIST [11] . The advantages of MBIST are simplicity of test program, Possibility to run different algorithm, Reduction in test cost, Possibility to run user defined algorithm on memories. Keyword: MBIST, MARCH C, MARCH A, MARCH B, MARCH 17n, MARCH 13n, PAA, DMO. Cite this Article A.M Aswin and S.Sankar Ganesh, Implementation and Validation of Memory Built in Self-Test (Mbist) – Survey, International Journal of Mechanical Engineering and Technology, 10(3), 2019, pp. 153-160. http://www.iaeme.com/IJMET/issues.asp?JType=IJMET&VType=10&IType=3 1. INTRODUCTION A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to test itself. Engineers design BISTs to meet requirements such as High Reliability, Low Repair cycle or constraints like limited technicians, cost of testing during manufacture [12]. A MBIST as the name suggests deals with in built embedded memory on the chip.It can deal with 8192 memories at a time. It supports ROM based testing. The difference between an MBIST and PBIST is that the PBIST can have one controller for handling a number of memories whereas an MBIST needs to have one controller for one memory. MBIST is a self- test logic that generates effective set of March Algorithms through inbuilt clock, data and http://www.iaeme.com/IJMET/index.asp 153 editor@iaeme.com
A.M Aswin and S.Sankar Ganesh address generator and read/write controller to detect possibly all faults that could be present inside a typical RAM cell whether it is stuck at 0/1 or slow to rise, slow to fall transition faults or coupling faults [11]. MBIST commonly works with MARCH C Algorithm. The Fig.1 gives the basic mechanism of MBIST. The controller is accessed through Test Access Port which gives the basic input like clock etc., to the controller. The controller access the memory through an Interface. The controller writes the memory and reads the data. The comparison will be made in the controller. There will be an interface between the controller and the memory. The MBIST works with user defined algorithm also this is an added advantage in MBIST. Figure 1: Basic Mechanism 2. PROPOSED SYSTEM Our paper consists of different methods to implement and validate MBIST in different applications and increase the efficiency. All the methods we have mentioned in this paper is unique for specific application. These methods cannot be compared one with another. So these methods are unique and will be helpful in MBIST implementation and validation in those specific applications 3. ALGORITHMS The Algorithms used in MBIST are to identify faults. The common faults that can occur in a memory includes stuck at 0 faults, Stuck at 1 faults, Data retention faults etc. All the algorithms cannot be used to identify all the faults. Certain algorithms identify certain faults. Therefore depending on the fault that may occur in a specific memory we can choose the Algorithms.  March C  March A  March B  March 13n 4. LITERATURE SURVEY ALGORITHM ADVANTAG TITLE PROBLEM STATEMENT APPLICATION RESULT USED E A new P-MBIST with Less the aim of merging number of Optimal Programmable MBIST the FSM and states March C lower area Merging FSM and microcode required in March X Embedded overhead Microcode Techniques architecture using March A Memories in SOCs from the its Using Macro Commands macro-commands is March B read/write [2] previous P- proposed. The hybrid operation MBISTs. P-MBIST utilizes the state- same macro- machines http://www.iaeme.com/IJMET/index.asp 154 editor@iaeme.com
Implementation and Validation of Memory Built in Self-Test (Mbist) – Survey commands for compared selecting the test to the algorithm and same previous P- encoding technique MBIST for the MARCH elements but instead of using state machines, it is designed by implementing clusters of microcode to control the read/write operation and test data injection. The rapid development of internet andtelecommunicatio n, video compression becomes more and more important. The result H.264/AVC integrates showed that the Due to BIST MBIST design and MBIST achieved controller implementation of a high resolution, high Video decoder March17n 100% fault reuse, circuit H.264/AVC video decoder compression ratio, chip coverage by a area was chip [3] and became one of the 2.49% increase saved. most popular in chip area. protocol. Therefore, the H.264/AVC decoder chip is a preferred answer for low cost system integration. The experiments show the ability EDA industry is see-king of the maintenance TMBValidator methodologies to support to verify various its software, and to controller improve the overall quality features. Quality Assurance in Increased of tools as they are User defined Commercial Demonstrate its flexibility and Memory Built-In Self-Test affecting customer Algorithms memory BIST tool versatility to Tools [5] efficacy satisfaction.Monitorig determine activities of tools and reliably the test detectingpostdevelopment coverage when software errors cannot be working with a overestimated. variety of memory fault models. PROBLEM ALGORITHM APPLICATIO TITLE RESULT ADVANTAGE STATEMENT USED N The Current With the The proposed Implementation March proposed March scheme is more of March Algorithm with March algorithm all the efficient in terms Algorithm Based To test SRAM 22 N is Algorithm with general of circuit size and MBIST chips inefficient in 13 N. occurring faults test data to be Architecture for certain cases to identified and applied, and it SRAM [7]. make a full are diagnosed. requires less time http://www.iaeme.com/IJMET/index.asp 155 editor@iaeme.com
A.M Aswin and S.Sankar Ganesh diagnosis of March test to test SRAM SRAM. algorithms and chip. the simulation results have shown that 100% fault coverage and 100% diagnostic resolution has been achieved. The area occupied by embedded recollections in System-on-Chip (SoC) is over 90%, and expected to elevate up to 94% by 2014. DESIGN AND Thus, the ANALAYSIS performance OF MARCH C and yield of BISR occupies Occupies lesser ALGORITHM embedded Embedded March C 20% area and Space FOR COUNTER recollections Memories in Algorithm can work at up BASED will dominate common. Higher Efficiency to 150MHz. MBIST that of SoCs. CONTROLLER SRAM is more [8]. expensive and less dense than DRAM and is therefore not used for high- capacity, low- cost applications such as the main memory in personal computers. SOCs comprise of wide range of memory The proposed modules so it is architecture not possible to achieves Low Cost test all the SOCs Programmable FSM Module improved test memory Comprising Increase in FSM based selects the better flexibility, lower modules with wide range of Flexibility MBIST suitable testing cost, the help of a memory Architecture [9] algorithm. high frequency Overhead is single modules. reduced and the algorithm. Each overhead is memory type reduced may require a distinct test algorithm. http://www.iaeme.com/IJMET/index.asp 156 editor@iaeme.com
Implementation and Validation of Memory Built in Self-Test (Mbist) – Survey Implementing an MBIST to test each memory module would result in a high production cost; hence it makes more sense to use a programmable MBIST for entire chip instead of using it for individual memory modules. .a) Decreases Test SOCs Time. BIST Architecture Testing multiple for Multiple RAMs March C containing The Testing Memory cores in SOC [10] Algorithm multiple Time is reduced. b) Increases Fault in parallel memory cores. Coverage PROBLEM ALGORITHM APPLICATIO TITLE RESULTS ADVANTAGES STATEMENT USED N Programmable BIST approaches, allowing selecting after Extended fabrication a programmable large variety of BIST to memory tests, complete are therefore programmability desirable, but . This new may lead on feature is Memory Testing unacceptable implemented at and Repairing area cost. BIST low cost by Using MBIST approaches Socs using using the Low Cost with Complete enabling test March C Programmable memory under Programmability algorithm Algorithm Bist test itself to . [4] programmabilit store the desired y and data address background sequence and programmabilit some compact y at low area circuitry that cost have been enables using presented in the this sequence past. However, for testing the no proposals memory. exist for programming the address sequence used by the test http://www.iaeme.com/IJMET/index.asp 157 editor@iaeme.com
A.M Aswin and S.Sankar Ganesh algorithm. Currently, the area engaged by memories which are embedded is more than 90.0%, and estimated to increase up to more than 95%. Performance and output will lead chip technology in the case of embedded memories. EFFICIENT However, MEMORY memory PA algorithm BUILT - IN production efficiently SELF TEST output is Embedded detects probable Detects more FOR restricted more PA Algorithm SRAM number of fault number of faults. EMBEDDED by random Memories models compare SRAM USING defects, to other March PAALGORITH processing over test algorithms. M [1] the gross and construct faults, processing for specific faults other defects and faults. To increase the consistency and output of memories, many algorithms and mechanism. In both prolixity columns and rows are integrated into the array of memory. The entire Greater than Design For functional IO 98% stuck-at Testability space of the test coverage. Features of the chip is high Embedded SUN speed SERDES Niagara2 SRAMs are Efficiency DMO Microsystems rendering SPARC chip covered Speed Niagara2 testing with completely by CMP/CMT functional at-speed MBIST SPARC Chip [6] vectors difficult equipped with a and limited. rich feature set http://www.iaeme.com/IJMET/index.asp 158 editor@iaeme.com
Implementation and Validation of Memory Built in Self-Test (Mbist) – Survey This supporting makes providing debug, high quality bitmapping, and stuck-at and failure analysis. transition test vectors imperative. 5. CONCLUSION: The Validation and Implementation of MBIST occurring in different applications are studied and the different ways by which cost can be reduced and different ways to improve the efficiency of the system is also studied. REFERENCES [1] G.PRAKASH, M.Tech, School of Computing , S.SARAVANAN, Assistant Professor, SASTRA University, Thanjavur, “EFFICIENT MEMORY BUILT – IN SELF TESTFOR EMBEDDED SRAM USING PAALGORITHM “ on International Journal of Engineering and Technology (IJET), Vol 5 No 2 Apr-May 2013 pp.944-948. [2] Phond Phunchongharn, Dusit Niyato, Member, IEEE, Ekram Hossain, Senior Member, IEEE, and Sergio Camorlinga, “An EMI-Aware Prioritized Wireless Access Scheme for e-Health Applications in Hospital Environments”, in IEEE TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE, VOL. 14, NO. 5, SEPTEMBER 2010, pp.1247-1258. [3] Ligang HOU, Wuchen WU, VLSI &System Lab, Beijing University of TechnologyBeijing,China,JiahuiZhuHSC-DACDept.Analog Devices Inc. Beijing, Design CenterBeijing, China, “MBIST design and implementation of a H.264/AVC video decoder chip”on 2nd International Conference on Signal Processing Systems (ICSPS), pp.V1.87-V1.90 [4] Darsi Koteswaramma, E.C.E, Aditya Engineering College, India K.MuraliKrishna, Sr.Assistant Professor E.C.E, Aditya Engineering College, India Dr. M .Sailaja, professor, E.C.E, university college of Engineering, JNTUK, India, U.Yedukondalu, Head & Associate professor E.C.E, Aditya Engineering College, India, “Memory Testing and Repairing Using MBIST with Complete Programmability” in IOSR Journal of Electronics and Communication Engineering (IOSR-JECE),Volume 9, Issue 2, PP 80-83 . [5] Albert Au, Artur PogielJanusz Rajski, Piotr Sydow MentorGraphicsCorporation, Wilsonville, Jerzy Tyszer, Justyna Zawada, Poznań University of Technology, Poland “Quality Assurance in Memory Built-In Self-Test Tools” in IEEE Journal,pp.741-759 [6] Robert Molyneaux, Tom Ziaja, Hong Kim,Shahryar Aryani, Sungbae Hwang, Alex Hsieh, SUN Microsystems “Design For Testability Features of the SUN MicrosystemsNiagara2CMP/CMT SPARC Chip” in INTERNATIONAL TEST CONFERENCE, pp.1-8 [7] M. Radha Rani, Vijetha Institute of Technology, G. Rajesh Kumar, G. PrasannaKumar, and Sciences, Vishnu Institute of Technology, “Implementation of March Algorithm Based MBISTArchitecture for SRAM” in International Journal of Advanced Research in Computer Engineering & Technology Volume 1, Issue 3, May2012 2015,pp.250-253. [8] T.V.Sirisha, II year, M.Tech VLSI system design, T. Vasu Deva Reddy, B.E, M.Tech(Ph.D.), Department of ECE, AssociateProfessor, B V Raju Institute of Technology, Hyderabad, “DESIGN AND ANALAYSIS OF MARCH C ALGORITHM FORCOUNTER BASED MBIST CONTROLLER” , International Journal For Technological Research In Engineering Volume 3, Issue 3, November-2015, pp.376-380. http://www.iaeme.com/IJMET/index.asp 159 editor@iaeme.com
A.M Aswin and S.Sankar Ganesh [9] Sonal Sharma,Vishal Moyal, “Programmable FSM based MBIST Architecture” in International Journal of Digital Application & Contemporary research, Volume 1, Issue 7, February 2013, pp.263-275. [10] Preethy K John, Rony Antony P, “BIST Architecture for Multiple RAMs in SoC” on Procedia Computer Science Volume 115, 2017 pp.159-165. [11] https://www.edn.com/design/integrated-circuit-design/4432284/MBIST-verification-- Best-practices---challenges. [12] https://en.wikipedia.org/wiki/Built-in_self-test http://www.iaeme.com/IJMET/index.asp 160 editor@iaeme.com