Model-Based Design for Embedded Systems- P25

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21 Smart Sensors Modeling Using VHDL-AMS for Microinstrument Implementation with a Distributed Architecture Carles Ferrer, Laura Barrachina-Saralegui, and Bibiana Lorente-Alvarez CONTENTS 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 21.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 21.3 Design Methodology for MEMS Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 21.4 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 21.5 Accelerometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 21.5.1 Description of the Accelerometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 21.5.2 Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 21.5.3 IBIS Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 21.5.4 Interface of the Accelerometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 21.6 Gyroscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 21.7 Smart Sensor Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 21.7.1 IBIS Drivers in Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 21.7.2 Interface of the Gyroscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 21.8 Simulation and Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 21.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 21.1 Introduction The growing importance of microelectromechanical systems (MEMS) in a wide range of applications, which combine extreme sensitivity, accuracy, and compactness, has evidenced the need to simplify the design process in order to reduce the design time and cost. One of the possible solu- tions for MEMS design is the extension of the use of an integrated circuit design methodology to obtain a top-down design methodology that is pos- sible thanks to the new available mixed-signal modeling languages, such as VHDL-AMS [1], analog and mixed-signal extension of VHDL language, 697
698 Model-Based Design for Embedded Systems which allows developing models that combine not only digital and analog signals, but also thermal, mechanical, and optical signals. The main step in the process of designing for MEMS integration is to com- bine VHDL models with VHDL-AMS models to obtain a complete descrip- tion of the multitechnological system. Considering a simplified design flow for mixed-signal models, the first step will be to define initial specifica- tions including environment and technical characteristics. The next step is to define interfaces and partitioning into basic components (including sensors, actuators, analog, and digital circuitry) to design an abstract structure that meets the initial requirements. Each component modeling is realized with the most appropriate language and could be described at different represen- tation levels (behavioral, structural, circuit, device, and physical) [2,3]. The modeling of each component becomes a complex task because of the differ- ent languages and abstraction levels required. Finally, after the fabrication and/or assembly of all the components, a test and qualification phase must be carried out in order to guaranty the expected quality levels for the target application. In one approach, the digital elements have been developed by using VHDL, while the nonelectronic (transducers) parts and the analog and mixed-signal circuitry models have been elaborated in VHDL-AMS. The microinstrument that is modeled and to which this methodology is applied is an inertial measurement unit (IMU). An IMU is the main com- ponent of inertial guidance systems used in air-, space-, and watercraft. An IMU works by sensing motion including the type, rate, and direction of that motion, and it will be composed of three accelerometers and three gyro- scopes with all these transducers based on MEMS technology. Additionally, the necessary processing circuitry and modules for digital communication have to be treated and modeled with the most suitable language depending on the nature of the element. This chapter is structured in the following manner: Section 21.2 presents the distributed architecture; Section 21.3 deals with the design methodology for MEMS; Section 21.4 provides an example of an application case based on an IMU; Sections 21.5 and 21.6 present accelerometer and gyroscope sensor modeling, respectively; Section 21.7 describes the modeling of a complete smart sensor including the sensor and their associated electronic circuitry; Section 21.8 presents simulation and validation results; and Section 21.9 concludes the chapter. 21.2 Architecture The associated electronic circuitry that measures a sensor must be considered, and it adds different and necessary functions, such as correcting offsets, temperature compensations, AD conversions, etc. All these functions
Smart Sensors Modeling Using VHDL-AMS 699 Signal conditioning Amplification Driver Processing Sensors Driver Microcontroller Driver Amplification Processing Actuators Driver FIGURE 21.1 Distributed architecture. have to be considered from early design phases of a smart sensor. Smart microsystems can not only process the signal coming from the sensor itself, they can also have the communication drivers related to these sensors [4]. All nodes or the set of smart sensors are connected to a host (com- puter or microcontroller) through a sensor bus called interconnection bus for integrated sensors (IBIS). IBIS was designed for a better serial connec- tion between the smart sensors and the main controller. The communications between nodes is established through a designed protocol where each node is classified into master or slave and has its own logic address [5]. This bus is based on a distributed architecture (see Figure 21.1). The main advantage of the distributed architecture is that when it has to be extended because of the increasing number of smart sensors or actuators in a microsys- tem, additional smart sensors or actuators can easily be connected without the need to rearchitect. So, one of the solutions found was to specify a dis- tributed architecture in which a bus sensor was implemented, and this way a specific interconnection was developed [6]. The distributed architecture introduces the advantage of modularity and interchangeability as it enables an easy communication applicable to differ- ent sets of microsystems. Its main characteristic is to own two buses. The sensor bus is used for relatively short distances, a few centimeters, and for connecting sensors and actuators on the same subsystem through a dedi- cated microcontroller. The use of miniature sensors in high numbers raises the problem of the size and mass of the interfacing cables and connectors, which are currently much higher than those of the sensors themselves. This increases the necessity to address the problem of whether it is possible to reduce, or even eliminate, the mass and volume of the interfacing devices. An evolution of this second architecture can be seen in Figure 21.2. It is shown how the master is combined with several elements such as
700 Model-Based Design for Embedded Systems S/A + circuitry Several interfaces Processor Master Host S/A + circuitry Memory S/A + circuitry SoC bus Sensor bus Application bus (IBIS) Micro instrument level SoC level Application level FIGURE 21.2 Enlarging the architecture. memory, processor, and interfaces, forming a system on chip (SoC) that could be implemented with an ASIC or an FPGA, and how they can be inte- grated in the distributed architecture, combined with a higher lever (appli- cation level) and the lower level (sensor level) to built up the instrument. As it is said, IBIS was designed for the better integration of the sensors in a system. We have decided to create a two-wire low rate synchronous mono- master bus. This bus can address up to 31 slaves, using the 32nd address to address all the slaves at the same time, when it is necessary to send a general reset, to do a self-test, or to initialize the sensors and actuators at the same time specially. However, any new necessary command that will affect the entire system could be implemented. The speed of an IBIS is about 1 MHz, and it has a bus-shaped topology. 21.3 Design Methodology for MEMS Design The design of MEMS can often become a task more complex than design- ing an electronic circuit. This is because MEMS behavior cannot be consid- ered a simple addition of separate mixed (fluidic, optical, thermal, etc.) and electrical behavior, but it is a simultaneous combination. This fact motivates the extension of the existent design methodology for integrated circuits to obtain a top-down design methodology for MEMS design [7]. It is based on a hierarchical design method with both abstract behavioral and functional models in device-analog-digital domain (see Figure 21.3). The development of a design hierarchy allows the designer to mix levels of abstraction to observe and evaluate interactions between interdependent subsystems.
Design of the system mixed signal verification Specifications Defining interfaces Sensor/ Analog Digital actuator Behavioral model Behavioral model Behavioral model S/A block design analog block digital block design Partitioning design Block Block Function specifications specifications synthesis Detailed design Functional model Functional S/A structural Functional model model device design functional RTL level design Fabrication or Device Macro Logic programming specifications specifications synthesis Fabrication description Spice description Gate description Assembly wafer level transistor level gate level design design design (if necessary) Smart Sensors Modeling Using VHDL-AMS Physical design Physical design Physical design Test and qualification FIGURE 21.3 Top-down design flow for MEMS. 701
702 Model-Based Design for Embedded Systems In this design flow, the functionality can be easily verified and analyzed at the top level. The specifications and characteristics of each stage (sensor/ actuator, analog, digital) can be fixed at a lower level, using specific simu- lators (such as SPICE for analog circuits) to optimize design at the lowest level blocks. This phase is very close to the convectional methods used in MEMS design. The following phases of the design include effects because of the extension of a top-down “digital” methodology: (a) The verification of the whole simulation system can be obtained, although it is not possible to directly synthesize the complete design with VHDL-AMS. (b) Rapid and easy design process from the top-down. We take physical characterization into consideration at the final design to validate abstract models developed in early design stages. (c) Evaluation of the entire system at any design stage. This is of greater importance in the analog and MEMS design, especially con- sidering the multitechnolgical nature of MEMS. In order to obtain the necessary models of the MEMS, there are sev- eral possible approaches. Generalized networks can be considered in MEMS modeling because many physical quantities are compared to flow or differ- ence quantities and generalized Kirchhoff’s laws can be applied. To obtain a generalized network, large systems can be interpreted as decompositions into basic network elements. This network concept is valid in many different domains, such as electrical, fluidic, mechanical, etc. Another way to obtain the model is using order reduction. Modeling strategy with the real system can be described using partial differential equations for the entire system; producing reduced system matrices that simplify the simulation effort required comparing with the complexity of the equations that describes the MEMS device functionality. The last way is to obtain behavioral models as black-box models, derived from simula- tion results in the time or frequency domain. Once the model is developed and included in the complete system, the simulation process must consider a tuning phase through the optimization of parameter settings. The available modeling tools as well as available multidomain libraries are usually incomplete. However, many system simulators can support stan- dardized modeling languages, like VHDL-AMS, and therefore any others in the near future. 21.4 Application The case example presented in this work focuses on the development of a complete behavioral model of an IMU in VHDL-AMS. This IMU com- bines MEMS sensing technology with analog and digital signal processing circuitry, all interconnected in a distributed architecture through the bus IBIS. The system is composed of three accelerometers and three gyroscopes, one for each direction of space, its conditioning signal circuitry, and the
Smart Sensors Modeling Using VHDL-AMS 703 corresponding interfaces to connect them to the communication bus. The complete system model covers mixed-technology sensors and mixed-signal circuitry, so it has been developed in VHDL-AMS for the analog and mixed- technology modules, and VHDL for the digital ones. All these models have been cosimulated within the same environment following the design methodology design flow described in Figure 21.3. In this approach, a behav- ioral description of sensor/actuator and analog circuitry has been chosen in combination with a more structural description of the digital circuitry parts. By employing an IMU, it is possible to know the position of an object in motion, so it has many applications in remote control systems and navigation systems. An IMU may have many architectures and designs, with different composing elements, depending on the technology and algorithm employed. In our case, the IMU is composed of three accelerometers and three gyro- scopes, each one with its own processing signal circuitry, although it could be designed using a Kalman filter and gyroscopes. Both designs have been corrected from early conception to provide an adequate response for the analog-to-digital converter (ADC). They are basically composed of an ampli- fier stage and filtering modules to reduce the electrical noise. Finally, to con- nect each sensor to the communication bus, it has been necessary to develop an interface to synchronize and make the data types compatible. The IMU structure is shown in Figure 21.4. X-axis IBIS Accelerometer Output circuitry Interface Gyroscope Output circuitry Interface SoC bus Y-axis Communication interfaces Accelerometer Output circuitry Interface Master Processor Gyroscope Output circuitry Interface Memory Z-axis Accelerometer Output circuitry Interface Gyroscope Output circuitry Interface FIGURE 21.4 IMU structure.
704 Model-Based Design for Embedded Systems Different models have been elaborated for each element of the system, trying to develop behavioral and functional models to be employed in large simulations, and structural models that allow descending to lower levels of abstraction. In this way, we obtain a complete description of the system, and it is thus possible to compare the results of both models in order to improve them and use the most suitable model in each simulation. 21.5 Accelerometer The accelerometer that has been assembled as a part of the IMU can be con- sidered a smart sensor, since it contains the necessary additional circuitry to connect it to a main controller digital system. The smart sensor is composed of the acceleration sensor, its output circuitry with an analog-to-digital con- version, and an interface to adapt the system to a digital device. Its internal structure is shown in Figure 21.5. 21.5.1 Description of the Accelerometer The accelerometer is based on the piezoresistive effect, and was built into an SOI (silicon-on-insulator) wafer packaged on an MCM [8]. It is a Wheatstone bridge with four piezoresistances placed on a cantilever design, whose value will depend on the direction of the applied acceleration. We have devel- oped three different representations of this accelerometer, which will be used depending on the level of abstraction and the features that we want to study. The three models are a behavioral model, a physical model, and a mathemat- ical model. • The behavioral model of the accelerometer is a simple model that shows a linear relation between the applied acceleration and the output voltage. The equation used has been obtained based on the experimental measurement. This simple model is useful to test other IBIS S&H CHS + Interface ADC Amplifier stage Accelerometer Output circuitry FIGURE 21.5 Complete system schematic.
Smart Sensors Modeling Using VHDL-AMS 705 elements of the sensor, and also to perform simulations that involve several accelerometers. These simulations could take much time and resources of the simulator. The model with its simulation can be seen in Figures 21.6 and 21.7. • The physical model of the accelerometer takes care of the piezoresistive effect in the Wheatstone bridge. Given an acceleration, it first calculates all of the stress applied to the resistances because of this acceleration, depending on the direction that each resistance is placed. The relation between the acceleration and the stress is modeled as a linear relation, whose constants can be obtained through experimental measurement. Considering the stress applied to each resistance, the next step is calcu- lating the change in the resistive value. This computation is performed by applying the known constants for the piezoresistive material of sili- con for 100 wafers. With this data, the output voltage of the Wheatstone bridge is easily obtained by applying the characteristic equations of the system. entity acc 2_5 v1 is generic (--------Default values for the generics are from D ZU-25g--------------------------- ----------------------------------------------------------------------------------------------------------------------------- ----------Static characteristics-------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- Z_in :real = 1888e3; --[Input impedance] = Ohms Z_out :real = 1882e3; --[Output impedance] = Ohms Offset :real = 0.00510; --[Offset] = V/V S_sens :real = 0.00046; --[Sensitivity] = V/(V.G) Vdd :real = 5.0; --[Voltage supply] = V N_lin :real = 037; --[Non-linearity] = %PSO Hyst :real = 0.12; --[Hysteresis] = %PSO Repet :real = 0.14; --[Repetibility] = %PSO C_sens_x:real = 693; --[X axis cross sensitivity] = % FIGURE 21.6 Behavioral model for the accelerometer.
706 Model-Based Design for Embedded Systems 1.2 1.0 S (test_acc2_5vl : yacc:a_in) 0.8 0.6 0.4 Y values 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 2.5 m 2.0 m S (test_acc2_5vl : yacc:v_out) 1.5 m 1.0 m 0.5 m EMF (V) 0.0 m –0.5 m –1.0 m –1.5 m –2.0 m –2.5 m 0.0 m 10.0 m 20.0 m 30.0 m 40.0 m 50.0 m 60.0 m 70.0 m 80.0 m 90.0 m 100.0 m 110.0 m Time (s) FIGURE 21.7 Simulation of the accelerometer behavioral model. • The mathematical model describes the accelerometer as a mass-spring system. It applies the Newton’s second law, which also deals with the damping force. Again, the constants used have been obtained through experimental measurement and known physical values. This model shows the possibilities of VHDL-AMS of solving differential equations. 21.5.2 Output Circuitry The output circuitry of the accelerometer can be treated separately in two parts. The first one is the signal conditioning circuitry based on Chopper stabilization (CHS), so it amplifies the signal and eliminates the noise. The second part consists of a sample and hold (SH) device and an ADC, and makes possible the connection of the sensor to a digital device. The entire system scheme can be seen in Figure 21.8. First, we address the signal conditioning circuitry. The operation princi- ple in CHS is to avoid low level noise by moving the signal to higher fre- quencies and restoring it to its original frequency once amplified. The output voltage of the accelerometer reaches the first modulator, so it is transferred to the frequency imposed by the oscillator. The next step is to amplify the signal and pass through a band-pass filter, in order to eliminate undesirable signals.
Smart Sensors Modeling Using VHDL-AMS 707 CHS Oscillator Vin Vout A ×1 ADC Input Output modulator Pre- modulator Buffer Sample and amplification Passband Low pass hold filter filter FIGURE 21.8 Accelerometer output circuitry. Finally, the second modulator and the low-pass filter restore the original fre- quency signal. The signal conditioning circuitry is composed of two modulators (input/output, which are controlled by an oscillator signal), a preamplifi- cation, a band-pass filter, an oscillator, a low-pass filter (40 dB/decade and 10 kHz Butterworth filter), and a frequency divider. The oscillator is composed of an astable multivibrator (square-wave generator) and a comparator. It was designed to obtain the filter resonance frequency and oscillator frequency as closely as possible. The frequency of oscillation is defined by the relation between R0 and R1 (see Figure 21.9) and presents a value of 110 kHz. In spite of developing this model according to its schematic, its simulation has not been successful because it is impossible to define initial conditions on the simulator. For the global system simulation, a behavioral model of the oscillator has been used (Figure 21.10). The modulator is composed of different logic gates (see Figure 21.11) and provides two square signals with the frequency of the oscillator, with a delay of 180˚ between them. The preamplifier presents a gain of 100 dB, and it is composed of a differ- ential amplifier with two amplification stages (see Figure 21.12). The low-pass filter is a differential filter based on a 40 dB/decade But- terworth filter. The cutoff frequency of the filter is 10 kHz, and the model developed and the simulation results of the filter can be seen in Figures 21.9 and 21.10. The band-pass filter is a differential filter based on a narrow band’s band- pass filter (see Figure 21.13). The most important characteristics are the res- onance frequency of 110 kHz, which is the frequency of the oscillator, and a 40 kHz bandwidth. These features can be seen in the results shown in Figure 21.14. For this simulation, the behavioral description of the accelerometer has been used as excitation signal. As can be seen in Figure 21.15, the output signal has a linear relation with the input signal, and amplifies it in two orders of magnitude.
708 Model-Based Design for Embedded Systems C0 R0_1 4 2 V– – 1 R0 R0 Out Vout1 3 Vin+ + 8 C1 V+ Vdd ref R1 R1 C1 U2A8 V+ Vout2 3 Vin – + 1 Out 2 – 4 V– R1_1 C1 FIGURE 21.9 Schematic corresponding to the low-pass filter. Next step is to model the second part of the output circuitry, which con- sists of an SH circuit and an ADC. Between these elements and the amplifier output circuitry simulated before, a simple buffer had to be added to make the offset levels compatible. The SH circuitry is based on a simple design with only one capacitor, where the sample is controlled by a switch and its clock signal. The converter operation is controlled also by a clock signal, which is the clock signal used by the IBIS bus. Its simulation can be seen in Figure 21.16, where the transformation of analog data to digital data is shown. The synchronization between the IBIS and these elements is achieved through an interface, which allows the connection between the digital and the analog parts of this smart sensor. In Figure 21.16 the first signal shown is the excitation signal, followed by the same signal sampled, and finally intermediate signals that synchro- nize both elements. The command signal governs the beginning of the data capture, which finishes when the dout signal takes a value. 21.5.3 IBIS Drivers All the developed IBIS drivers have a similar inside structure. The bus codi- fication is done in Manchester encoding, this allows a better transmission and its synchronization, but has the drawback of making the driver slightly more difficult to develop. The drivers are necessary to connect the slaves with the master of the bus, and they all are formed by different modules that
0.0 VDB (test_1p : v_out1) –20.0 VDB (test_1p : v_out2) –40.0 –60.0 –80.0 –100.0 –120.0 –140.0 Magnitude (dB) –160.0 –180.0 –200.0 –220.0 200.0 VP (test_1p : v_out1) VP (test_1p : v_out2) 150.0 100.0 50.0 0.0 –50.0 Phase (degrees) –100.0 Smart Sensors Modeling Using VHDL-AMS –150.0 –200.0 2 3 4 56 2 3 4 56 2 3 4 56 2 3 4 56 2 3 4 56 2 3 4 56 1.0e + 3 1.0e + 4 1.0e + 5 1.0e + 6 1.0e + 7 1.0e + 8 1.0 Frequency (Hz) FIGURE 21.10 Results obtained for the low-pass filter. 709
710 Model-Based Design for Embedded Systems clk1 1 1n clkin 3 1 2 1 2 2 1 NOR2 INV INV INV 2 1 3 1 2 1 2 2 NOR2 C2 INV INV 1n clk2 FIGURE 21.11 Schematic corresponding to the modulator. Vdd Vdd 11 3 V– 11 Vin+ + 1 3 V– Out + 2 1 – Out Vout+ 4 2 – 4 V+ R5 R8 V+ R6 R9 4 R10 R7 2 V+ – 4 2 1 V+ – Out Vout– 1 3 Out + 11 3 V– Vin– + 11 Vdd V– Vdd FIGURE 21.12 Schematic corresponding to the preamplifier. comprise different functions, as for example, a fragmentation module, a Manchester encoding module, a Manchester decoding module, a module of frame formation, and all the involved mechanisms for the appropriate bus interaction. Examples of the later are the frequency divider or the intern buffers, to ensure that the data is not lost. Furthermore, the bus, because of its drivers, allows hot plugging and plug and play mode [9,10].
Smart Sensors Modeling Using VHDL-AMS 711 C4 R1 4 R2 C3 2 V+ Vin+ – R1 1 Out Vout+ 3 + 11 Vdd V– Ref 11 Vdd 3 V– + R1 1 Out Vout– R3 C5 2 Vin– – 4 R4 U11A V+ C6 FIGURE 21.13 Schematic corresponding to the band-pass filter. For easier design, all has been included in one single IP. Each device has a physical address programmed in it, and, as it has been said before, an IBIS can have up to 31 slaves. In Figure 21.17 we can observe the structure of a connection between the driver and the master of the bus; the shaded part depicts the IBIS driver. 21.5.4 Interface of the Accelerometer To enable the connection between the digital part IBIS and the sensor, it is necessary to introduce an interface. Its main function is to receive commands from the IBIS and to synchronize the data acquisition according to these com- mands [11]. While not receiving any command or when it receives the reset command, the state of the system does not change. However, when the IBIS sends a command signal, the interface sends signals to the SH and the ADC to begin the data acquisition. The SH holds the signal while the ADC converts it to digital data. When conversion is finished, the ADC informs the interface and sends the digital data. The interface transmits the data to the IBIS bus and proceeds to wait for new commands. 21.6 Gyroscope Similar to the accelerometer, the assembled gyroscope itself can be consid- ered a smart sensor, since it is prepared to be connected to a digital device
712 0.0 VDB (test_bp : v_outp) VDB (test_bp : v_outn) –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 Magnitude (dB) –70.0 –80.0 –90.0 –100.0 160.0 VP (test_bp : v_outn) 140.0 VP (test_bp : v_outp) 120.0 100.0 80.0 60.0 40.0 20.0 0.0 –20.0 –40.0 Phase (degrees) –60.0 –80.0 –100.0 –120.0 Model-Based Design for Embedded Systems –140.0 –160.0 2 3 4 56 2 3 4 56 2 3 4 56 2 3 4 56 2 3 4 56 2 3 4 56 1.0e + 3 1.0e + 4 1.0e + 5 1.0e + 6 1.0e + 7 1.0e + 8 1.0 Frequency (Hz) FIGURE 21.14 Results obtained for the band-pass filter.
Smart Sensors Modeling Using VHDL-AMS 713 2.5 m 2.0 m S (test_sha: ylmea : out1 : vindif) 1.5 m 1.0 m 0.5 m EMF (V) 0.0 m –0.5 m –1.0 m –1.5 m –2.0 m –2.5 m 1.6 1.4 S (test_shad : ylmea : out1: voutacc) 1.2 1.0 0.8 0.6 0.4 EMF (V) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 0.0 m 2.0 m 4.0 m 6.0 m 8.0 m 10.0 m 12.0 m 14.0 m 16.0 m 18.0 m 20.0 m 22.0 m 24.0 m 2 Time (s) FIGURE 21.15 Simulation results obtained for the output circuitry. without the need to solve compatibility issues. Its structure is similar to the accelerometer, except that instead of the CHS amplification, the signal pro- cessing circuitry recommended by the manufacturer has been utilized. The smart sensor schematic is shown in Figure 21.18. The sensor employed is a gyroscope based on piezoelectric effects. It con- tains a ceramic bimorph vibrating unit, whose operating principle consists of the detection of the rotational motion from the generated Coriolis force. The ceramic material makes the bar vibrate, so when a rotational motion takes place, a Coriolis force is generated perpendicular to the original direction of vibration. This force is detected by other piezoelectric ceramics. The conditioning signal circuitry contains a high-pass filter with a cutoff frequency of 0.3 Hz, and a low-pass filter with a cutoff frequency of approx- imately 1 kHz. To adapt this signal to the SH and ADC devices, a condition- ing module has been added whose main objective is to amplify the signal to the range admitted by the ADC, and to make the offset levels compatible. This is achieved by means of a Zener diode and an operational amplifier. Its schematic can be seen in Figure 21.19. In order to connect the gyroscope to the IBIS bus, the same interface developed for the accelerometers has been used. The only difference between the interfaces is the address of which the sensor begins the acquisition.
714 Model-Based Design for Embedded Systems 3.2240 3.2235 V (test_shad : ylmea : v3) 3.2230 3.2225 3.2220 EMF (V) 3.2215 3.2210 3.2205 3.2200 3.2195 3.2190 3.2185 (a) 3.2240 3.2235 V (test_shad : ylmea : v4) 3.2230 3.2225 3.2220 EMF (V) 3.2215 3.2210 3.2205 3.2200 3.2195 3.2190 3.2185 (b) 0 0 0 0 + test_shad: ylmea: command + + + + + + + + + + test_shad: ylmea: start + + + + + + + + + + test_shad: ylmea: eoc x x x x + test_shad: ylmea: dout test_shad: ylmea: clk2 49.27 m 49.28 m 49.29 m 49.30 m 49.31 m 49.32 m 49.33 m 49.34 m 49.35 m 49.36 m (c) Times (s) FIGURE 21.16 Simulation of the signal capture. Analog Bus Sensor Converter Controller interface interface Bus FIGURE 21.17 Structure: Sensor + IBIS driver + controller. 21.7 Smart Sensor Simulation 21.7.1 IBIS Drivers in Sensors All the sensors and actuators need a specific driver to function properly, while the driver also implements the interface function with the dedicated
Smart Sensors Modeling Using VHDL-AMS 715 IBIS S&H + Interface ADC Signal processing Gyroscope circuitry Output circuitry FIGURE 21.18 Gyroscope smart sensor schematic. Vin Amplifier Amplifier stage Vout Vref Sample and ADC High-pass hold filter Low-pass filter FIGURE 21.19 Gyroscope output circuitry. bus sensors by containing the communication protocol. The implementation of the drivers has been developed in VHDL. The result has been validated in an FPGA, and the resulting IP model will be used in future developments based on the same bus sensor application. Two parts compose each driver: (a) the one for the specific communication with the sensor or actuator and its additional signal processing circuitry (this part is specific for each sensor, because it depends on the nature of it), and (b) the one that implements the communication bus protocol itself. These drivers are necessary to connect the slaves with the master of the bus and they are composed of different modules such as a fragmentation module, a Manchester encoding module, a Manchester decoding module, a module of frame formation, and all the involved mechanisms for a good operation of the bus. As an example we can mention the frequency divider or the intern buffers, to ensure that the data is not lost. As a result, the bus, because of its drivers, allows hot plugging and plug and play mode. 21.7.2 Interface of the Gyroscope The connection between the digital part of the IBIS bus and the sensor has been realized with the addition of an interface. Its main function is to receive commands from the IBIS and to synchronize the data acquisition according to these commands.