Model-Based Design for Embedded Systems- P26

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Model-Based Design for Embedded Systems- P26:The unparalleled flexibility of computation has been a key driver and feature bonanza in the development of a wide range of products across a broad and diverse spectrum of applications such as in the automotive aerospace, health care, consumer electronics, etc.

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726 Index specialization piecewise constant derivatives discrete functional category, 507 (PCD), 396 hybrid category, 509–510 time steps, 398 multi-viewpoint composition, model-based design, 383–384 512–515 modeling safety/probabilistic categories, discrete dynamics, 389–390 510–512 Lipschitz continuous, 390 semantic atoms, 507 non-determinism, 391 system architecture, 512 trajectories, 390–391 timed category, 507–509 rapidly-exploring random trees wrapper mechanism, 512 (RRTs) Hierarchical event streams (HESs) algorithm, 408–409 inner and output event streams, 71–73 hybrid distance, 410–411 structure, 71 iterations, 409–410 system analysis, 70–71 simulations, 409 HRC, see Heterogeneous rich component test generation (HRC) state machines algorithm, steps, 425 Hybrid approach cases and executions, 423–424 advantages and disadvantages, 35–36 continuous inputs, 422 basic block coverage-guided sampling, pipeline modeling, 40–43 425–426 principles, 39 discrete transitions, 422–423 static cycle calculation, 40 state coverage strategies, cycle prediction, dynamic correction 421–422 branch prediction, 43 test coverage, 424–425 cache analysis blocks, 44 testing, 411–412 cache model, 44 cycle calculation code, 45 I instruction cache, 43 IBIS, see Interconnection bus for objectives, 35 integrated sensors software tasks, 46–47 ICAP, see Internal configuration access SystemC code annotation, 38–40 port task switches, 46 IContinu, see Continuous domain WCET/BCET value, back-annotation interface, model advantages, 38 IDiscrete, see Discrete domain interface, architecture, 36–37 model instruction set, 37–38 Inertial measurement unit (IMU), 698, Hybrid automata 702, 703, 716, 717 exhaustive verification InitializeTA method, 469, 471 abstraction, 403–404 Input/output buffer (IOB), 368 autonomous linear systems, 398 Integrated multi-technology systems finite syntactic representation, abstraction levels, 608, 609 397–398 application, 622–631 linear inequalities, 397 CMOS transistor, 603–604 linear systems, 398–401 design productivity gap, 606 nonlinear systems, 401–403 ENIAC, 604–605 nontrivial differential equations, heterogeneous design methods, 396–397 639–640
Index 727 integrated optical interconnect BPT, 634–636 delay analysis, 632–634 link sizing method, 634 gate area analysis, 632, 633 power vs. interconnect length, 634, link specification set, 631 636 optical point-to-point link static and dynamic power, 637–638 synthesis, 623, 626–630 total power vs. interconnect performance metrics and length, 637 specification sets, 630–631 simulation and synthesis power analysis, 634–638 functional model, 622–623 simulation and synthesis, 622–623, optical device parameters, 623, 626 624–625 structural model, 622–623 simulation conditions, 632 UML class diagram, 623–625 synthesis procedures, 631 Verilog-AMS, 623 ITRS and design technology, 606–607 simulation conditions, 632 RuneII project synthesis procedures, 631 abstraction levels, 612–618 Interconnection bus for integrated design technology, 608, 610 sensors (IBIS) goals, 610–611 communications, 699 posteriori evaluation, 612 drivers, 708–711 priori generation, 612 sensors, 714–715 SoC/SiP design flow, 610–611 structure, 711, 714 system-level and physical-level Internal configuration access port phases, 611–612 (ICAP), 358, 370–372 UML/XML implementation, International technology roadmap for 618–622 semiconductors (ITRS), 520 several economic sectors, 604 Inverse discrete cosine transformation silicon and system complexity, 604, (IDCT) accelerator 606 address map and interfacing code, systems on chip (SoC), 603–604 222–223 Integrated optical interconnect interfacing code and interrupt delay analysis, 632–634, 635 handler code, 223–224 gate area analysis, 632, 633 macroblock decoding tasks, 221–222 link specification set, 631 types, 222 optical point-to-point link synthesis bit error rate (BER), 629 J classes-definition, 626, 628 Just-in-time (JIT) compilation, 31 CMOS circuit, 623, 626 Morikuni formula, 627, 629 L optical link sizing method, Linear electrical networks (LEN), 626–627, 629 588–589 photonic devices, 630 Linear multistep (LMS) methods, 575 physical implementation, 623, 627 Linear systems, hybrid automata scenarios, 628 autonomous, 398 schematic approach, 626 convex polyhedron, 399 transistor-level synthesis method, ellipsoids, 400 626–627 Minkowski sum, 400–401 performance metrics and reachability technique, 398–399 specification sets, 630–631 support functions, 399 power analysis zonotopes, 401
728 Index Linear temporal logic (LTL), 529 overview Linux behavior-performance EDK designs orthogonalization, 278–279 design constraints, 361–362 heterogeneous IP import, 278 device trees, 362–363 mapping specification, 279 managing partial reconfiguration semantics bitstreams, 372 mapping, 287–292 ICAP device, 370 required/provided ports, 287 reconfiguration process, 371 three-phase execution, 285–287 LOC, see Logic of constraints universal mobile telecommunications Logic of constraints (LOC) formula, system (UMTS) 276–277 architectural modeling, 304–306 Lookup tables (LUTs), 355 functional modeling, 301–303 Lower event-arrival function, η− , 61 mapped system, 306 results, 306–312 M METROPOLIS design environment MATLAB R , 22, 575 METROPOLIS meta-model (MMM) Memory-aware algorithms, 407 architecture modeling, 269–271 Message-passing interface (MPI), 208 function modeling, 268–269 Meta-variables, 99 mapping, 271–273 METRO II design environment recursive paradigm, platforms, academic approaches 273–275 BIP framework, 299–300 overview ForSyDe model, 298 design activities, 267 FunState, 300 syntactic and semantic MILAN, 296 mechanisms, 267–268 MoC/domains, 299 tools model-integrated computing formal property verification, (MIC), 295–296 276 Ptolemy II and SystemC-H, 297 LOC-monitor technique, design elements 276–277 adaptors, 284 quasi-static scheduling (QSS), 277 annotators and schedulers, 283 simulation, 275–276 components, 280–282 Micro-electrical-mechanical (MEM) constraint solvers, 282 systems mappers, 283–284 4f optoelectronic link, 666–667 overview, 281 BER vs. frequency, 668–669 ports, 282 Chatoyant analysis, 667–668 implementation, 280 CMOS drivers, 668 industrial approaches, 294–295 GLV system, 674–675 intelligent buildings grating light valve (GLV), 674–679 electronic control units (ECUs), insertion and crosstalk vs. mechanical 315 tolerancing, 668–669 function model and optical beam steering/alignment OpenModelica, 314–315 system, 668–674 goals, 313 vertical cavity surface emitting laser room temperature control system, (VCSEL), 667–668 313–314 Micro-elevator by self assembly (MESA) origin, 292–293 structure, 668–670
Index 729 Microelectromechanical systems globally asynchronous/locally (MEMS) synchronous, 561 design methodology, 700–702 heterogeneous systems, 560 VHDL-AMS, 697–698 models of computation (MoCs), Microinstrument implementation, see 560–561 Smart sensors modeling software implementation, 576–578 Mixed continuous and discrete systems synchronous/reactive models abstract semantics, 561 CountDown actor, 568 actor abstract semantics feedback system, 566 communication operations, multiclock SR model, 568, 569 565 postfire, prefire and fire, 567 postfire methods, 466, synchronous languages, 567 564–465 Mobile robots, sensor networks prefire and fire, 564–465 bus communication, 164 Ptolemy II models, 564 complete model, 165–167 setup, 564 evaluation, 167–168 Simulink S-function interface, hardware models, 161–163 563–564 physical scenario, 161 wrapup, 564 radio communication, 164–165 actor-oriented models simulation model, 160–161 abstract syntax, 562 software components, 160 atomic actors, 562 Model integrated computing (MIC), communication, 562–563 295–296, 464, 465, 473 composite actor and hierarchical Modeling and analysis framework abstraction, 561–562 computation model hierarchical abstraction, 562 execution traces, 132 priori configuration, 561–562 Huge State Space, 133–134 continuous-time (CT) dynamics hyper-periods, 133 ContinuousStepSizeController task characterization, 131 interface, 576 motivation Euler methods, 575 best-case and worst-case execution first-order differential equations, time, 124–125 573 cross-layer analysis, 124 MATLAB R , 575 multiprocessing timing anomaly, opaque composite actor, 576, 577 124–125 ordinary differential equations MoVES analysis framework (ODEs), 573 nondeterministic execution times, Runge-Kutta (RK) methods, 140 574–575 overview, 122–123 third-order nonlinear differential simple multicore embedded equation, 573–574 system, 136–137 discrete-event (DE) systems smart phones, 137–140 approaches, 568–569 stopwatch model, 140–141 event queue, 571 timed-automata model, 134 functions, 570 UPPAAL models mixed DE and SR model, 572–573 operating models, 123 modal model, 573 support, 135–136 setup phase/postfire method, multiprocessor system-on-chip 570–571 (MPSoC), 121
730 Index system-level models load variance (LV) statistics, application model, 126 200–201 execution platform model, 127–129 manual and static mapping, 199 illustration, 126 maximal communication (MC) memory and power model, statistics, 202 129–130 maximal load (ML) statistics, 201 task mapping, 129 total communication (TC) Models of computation (MoC), 522, statistics, 200–201 560–561 versions, 199 Modified nodal analysis (MNA), 650–652 causes, 180 Modular performance analysis, real-time MultiFlex mapping technology calculus developments, 186 characteristics, 17 iterative mapping flow, 186–187 component model, 14–15 streaming programming model, greedy shaper component (GSC), 16 187–188 modeling scheduling policies, 18 user-defined parallel applications, MPA framework, abstract 185 components, 15–16 MultiFlex streaming mapping flow system performance model, 16–17 abstraction levels, 189–190 transfer functions, 15–16 application constraints, 191 variability characterization curves functional capture, 190–191 (VCCs) high-level platform specification, arrival and service curves, 13–14 192 compact representation, 19–22 intermediate format, 192 MONTIUM system-on-chip model assumptions and distinctive average power consumption, 338 features, 192–194 design methodology, 335–336 MultiFlex streaming mapping tools heterogeneous, 336–338 component back-end compilation, partial dynamic reconfiguration, 339 197 reconfigurable processing core MpAssign tool, 194–195 communication and configuration MpCompose tool, 195–197 unit (CCU), 333–334 runtime support components, tile processor (TP), 334–335 197–198 reference locality, 338–339 parallel multiprocessor characteristics MoVES analysis framework heterogeneous composition, PE nondeterministic execution times, 140 types, 185 overview, 122–123 RISC-style processors, 184 simple multicore embedded system, platform programming models 136–137 advantages and drawbacks, smart phones, 137–140 182–184 stopwatch model, 140–141 classes, 182 timed-automata model, 134 explicit capture of parallelism, 184 UPPAAL models refinement and simulation, 202–203 operating models, 123 MPSoCs, see Multiprocessor support, 135–136 system-on-chip MPEG-2 video decoding tasks, 7 Multi-domain systems on chips MPSoC platform mapping tools (MDSoCs) 3G application mapping experiments Chatoyant multi-domain simulation, block diagram, 198 646–679
Index 731 HDL co-simulation environment, design criteria 680–689 dependability, 330 system simulation, 644–645 energy efficiency, 328–329 Multi-viewpoint state machines predictable and composable, components and contracts 327–328 assumptions, 491 programmability, 329–330 canonical form, 490, 492 heterogenous SoC template, 325–326, implementation, 490 327 parallel composition, 491 MONTIUM/ANNABELLE synchronization, 492–495 system-on-chip contract-based specification, 489 average power consumption, 338 extended state machines (ESMs) design methodology, 335–336 continuous dynamics, 495–496 heterogeneous, 336–338 definition, 496–497 partial dynamic reconfiguration, events and interactions, 495–496 339 input and outputs, 499 reconfigurable processing core, macrostates/locations, 501 333–335 openness, 500–501 reference locality, 338–339 product, 498 PACT-XPP projection, 497–498 architecture, 343–344 receptiveness, 499–500 design methodology, 344–345 runs, 497 streaming applications, 324–325 union/disjunction, 498–499 Tilera processor variables and ports, 495–496 design methodology, 346 heterogeneous rich component (HRC) features, 346 definition, 501–503 iMesh on-chip network, 346 labeling functions, 503–506 tile64, 345 specialization, 507–515 MultiFlex platform mapping technology original equipment manufacturers developments, 186 (OEM), 488 iterative mapping flow, 186–187 system design, 489 streaming programming model, Multicore architectures 187–188 advantages, 325–326 user-defined parallel applications, 185 Aspex Linedancer MultiFlex streaming mapping flow ASProCore architecture, 340–341 abstraction levels, 189–190 content addressable memory application constraints, 191 (CAM), 339–340 functional capture, 190–191 design methodology, 342 high-level platform specification, 192 hardware architecture, 341–342, intermediate format, 192 343 model assumptions and distinctive scalable architecture, 340–341 features, 192–194 SIMD architectures, 340 stages, 188 classification MultiFlex streaming mapping tools architectures, 332–333 component back-end compilation, 197 building blocks, 332 MpAssign tool, 194–195 flexibility vs. performance, 330–331 MpCompose tool, 195–197 interconnect structures, 332 runtime support components, multiprocessor system-on-chip 197–198 (MPSoC), 331–332 MultiFlex toolset, 186–187
732 Index Multiprocessor system-on-chip scanning mirror system, 669–670 (MPSoC), 331–332 scanning waveforms and diamond abstraction levels pattern, 670, 672 system architecture level, 242–243 scratch drive actuator (SDA), 669 transaction accurate architecture self-aligning system, 672–674 level, 244–245 Ordinary differential equations (ODEs), virtual architecture level, 243 573, 652, 654 virtual prototype level, 245 Original equipment manufacturers aggregate busy time, 68–69 (OEM), 488 event models, 65–66 formal performance analysis P deriving aggregate busy time, PACT-XPP, 343–345 68–69 Parallel multiprocessor, SoC platform deriving output event models, heterogeneous composition, PE types, 65–66 185 multicore component, 64 RISC-style processors, 184 response time analysis, 66–68 PBD, see Platform-based design hardware architecture, 235 PeaCE model, 220 hardware–software interface, 236–237 Picture-in-picture (PiP) application, 7–9 message passing organization, 234 Piecewise linear (PWL), 649 modeling and analysis framework, Platform-based design (PBD) and 121 frameworks modern hardware systems, 121 design challenge, 261 performance analysis loop, 63 METRO II design environment programming steps, 245–248 academic approaches, 295–300 aspects, 245 design elements, 279–284 description, 246–247 industrial approaches, 294–295 illustration, 246 intelligent buildings, 313–315 response time analysis, 66–68 origin, 292–293 shared memory organization, 234 overview, 278–279 Simulink R - and SystemC-based semantics, 284–292 programming, 245–248 universal mobile software architecture, 235–236 telecommunications system software development, 211–212 (UMTS), 301–313 tasks, 64–65 METROPOLIS design environment METROPOLIS meta-model N (MMM), 268–275 Negation as failure (NAF), 448–449 overview, 267–268 Non-deterministic finite automaton tools, 275–277 (NFA), 450 principles Noncausal methods, continuous definition, 262 execution model, 526 design parameters, 266 ns-2 discrete-event simulator, 148 flow concept, 263–264 fractal nature, 264–266 O productivity, 262 Open SystemC initiative (OSCI), 587 system-level design (SLD), 260 Optical beam steering/alignment system Predictive technology model (PTM), Chatoyant, 670–671 630–631 MESA structures, 668–670 Preemption, 101–102
Index 733 PriorityTA method, 470 RBbots Programming models, MPSoC hardware architecture, 163 H.264 encoder I2 C bus, 164 application and architecture types, 161–162 specification, 248–249 Retargetable, embedded software design system architecture level, 249–250 methodology transaction accurate architecture CIC programming model level, 253–254 architecture information file, virtual architecture level, 250–252 214–215 virtual prototype level, 254–256 description, 209 hardware architecture, 235 program generation, 211 hardware–software interface, task code, 212–214 236–237 CIC translator heterogeneous generic API translation, 216–217 design flow, 232–233 HW-interfacing code generation, processing units and 217 communication schemes, 231 OpenMP translator, 217–218 requirements, 232 scheduling code generation, software development platform, 218–220 232–233 workflow, 215–216 Simulink R - and SystemC-based experiments programming architecture, 220 abstraction levels, 241–245 design space exploration, 220–221 MPSoC programming steps, HW-interfacing code generation, 245–248 221–223 SoC design productivity analysis, 224–227 models, 238 scheduling code generation, primitives, 239 223–224 programming levels, 238 MPSoC software development, software architecture, 235–236 211–212 Proportional/integral/derivative (PID) parallel programming models controller, 462 characteristics, 210 Protothreads, 163 design productivity, 208–209 Ptolemy II design environment, 297 message-passing model, 208 Pure scheduling simulator, 148 MultiFlex MPSoC programming environment, 209 Q shared address-space model, 208 Quality of service (QoS), 513–515 SW architecture, 210 Quasi-static scheduling (QSS), 277 task-transaction-level (TTL) interface, 210 R Rich component models, see Rapidly-exploring random trees (RRTs) Multi-viewpoint state machines algorithm, 408–409 Robustness hybrid distance, 410–411 data quality, 80 iterations, 409–410 dynamic design robustness (DDR), simulations, 409 81–82 Ray tracing techniques, 659 evaluation and optimization, 80–81 Rayleigh–Sommerfeld formulation, 663, fault tolerance, 79 666 maintainability and extensibility, 80
734 Index reusability and modularity, 80 attributes, 100 static design robustness (SDR), 81 framework model RTC Toolbox abstract task and resource models, MATLAB libraries, 23 102–103 software architecture, 22 data structures, 103–104 RunCS_TA method, 472 resource template, 107–109 RuneII project scheduling policies, 109–112 abstraction levels task template, 104–107 AMS/MT hierarchy, 612–613, instantiation 614–615, 616 schedulability problem, 114–115 evaluation method, 617–618 schedulability query, 113 functional level, 613–614 modeling language IP design process, 615, 617 features and stopwatches, 99 modeling and structural timed computation tree logic hierarchies, 613 (TCTL), 99 single-level loop, 618 train-gate model, 96–98 synthesis method, 617 real-time model checking, 94 design technology, 608, 610 resources, 101–102 goals, 610–611 single-processor systems, 94 posteriori evaluation, 612 task dependencies, 100–101 priori generation, 612 time-triggered architecture (TTA), 94 SoC/SiP design flow, 610–611 Scratch drive actuator (SDA), 669 system-level and physical-level SDR, see Static design robustness phases, 611–612 Self-reconfiguring platform (SRP), UML/XML implementation 358–359, 360, 361, 363, 364, 368, AMS/MT IP blocks, 618–620, 622 372 class diagram, 620–621 Sensitivity analysis approach GUI flowchart, 618–619 characterization, 76–77 object management group (OMG), performance slack 618–619 modifications, 77 Runge-Kutta (RK) methods, 574–575 robustness optimization, 78 system dimensioning, 78 S Shared address-space model, 208 Scalar diffractive models SimEvents R 2 toolbox, 149 computation time vs. accuracy, Simics system, 149 662–663 Simple multicore embedded system, Helmholtz equation, 661 136–137 Maxwell equations, 659–660 Simulation interfaces modeling technique, 660 applications Rayleigh–Sommerfeld diffractive co-simulation framework, 549 formulation, 661–662 distribution, 538–539 valid propagation, 661–662 formalization and verification, wave equation, 661 539–546 Scenario-aware analysis internal architecture, definition, added and completed task, 74 546–549 compositional methodology, 75–76 library elements, 550 echo effect, 74–75 methodology unchanged task, 74 co-simulation framework, 530–531 Schedulability analysis, UPPAAL CTL and LTL, 529
Index 735 distribution, 528 dependability, 330 formalization, 529 energy efficiency, 328–329 internal architecture, 530 predictable and composable, 327–328 library elements, 531 programmability, 329–330 verification, 528–529 Streaming programming model Simulation-based approaches, 521–522 advantages and drawbacks, 182–183 Simulink R model, mobile robots, data-dominated applications, 187 158, 167 MultiFlex tool flow, 189 Simulink R - and SystemC-based objectives, 188 programming environment Structural semantics specification, MPSoc abstraction levels DSMLs system architecture level, 242–243 adding domain constraints transaction accurate architecture derived functions, 456–458 level, 244–245 NFA abstraction, 455 virtual architecture level, 243 compositions and domains virtual prototype level, 245 includes operator, 458–459 MPSoC programming steps operators, 458–459 aspects, 245 properties, 460–461 description, 246–247 pseudo-coproduct operator, 460 illustration, 246 pseudo-product operator, 459–460 Smart optical pixel transceiver (SPOT), renaming operator, 459 685–687, 688–689 domains and models Smart phones, 137–140 finite state machine (FSM), 449–450 Smart sensors modeling non-deterministic finite automaton accelerometer (NFA), 450 description, 704–706 types, 451 IBIS drivers, 708, 710–711, 714 expressive constraints interface, 711 definitions, 447 output circuitry, 706–708, 709, 710, domain constraints, 449 711, 712, 713, 714 expressions, 447 application, 702–704 LP approaches, 446–447 distributed architecture, 698–700 negation as failure (NAF), 448–449 gyroscope, 711, 713 queries, 449 microelectromechanical systems semantics, 448 (MEMS), 697–698 logic programming (LP), 444–445 design methodology, 700–702 metamodeling language, 443 simulation model contents and validation, 716, 717 boolean composition, 454–455 gyroscope, 715–717 negation as failure, 452–454 IBIS drivers, 714–715 queries, 451–452 VHDL-AMS models, 698 non-recursive and stratified, 445 SoC, see System-on-chip operations, 444 Software defined radio (SDR), 597–598 signatures and terms, 445 Static data flow (SDF), 646 syntax, 444 Static design robustness (SDR), 81 terms with types, 445–446 Stochastic automata networks (SAN), 30 Symmetric multiprocessor (SMP) model, Stopwatch model, 99, 140–141 182–183 Streaming applications System under test (SUT), 413–414, characteristics, 324–325 420–421
736 Index System-in-FPGA (SIF) architecture, 352 open SystemC initiative (OSCI), System-level models 588–591 application model, 126 refinement activities, 592, 594 execution platform model, 127–129 SystemC-based performance analysis illustration, 126 distributed embedded systems memory and power model, 129–130 analytical approaches, 29–30 performance analysis hybrid approaches, 31–32 analytic techniques, 6 simulative approaches, 30–31 design space exploration cycle, 4–5 experimental results, 47–50 distributed embedded platforms, 4 hybrid approach picture-in-picture (PiP) advantages and disadvantages, application, 7–9 35–36 simulation-based methods, 5–6 basic block, pipeline modelling, task mapping, 129 40–43 System-on-chip (SoC) dynamic correction, 43–45 ANNABELLE software tasks, 46–47 average power consumption, 338 static cycle calculation, 40 heterogeneous, 336–338 SystemC code annotation, 38–40 partial dynamic reconfiguration, task switches, 46 339 WCET/BCET value, 36–38 reference locality, 338–339 outlook, 50 integrated multi-technology systems, transaction-level modeling (TLM) 603–604 abstraction levels, 32 MONTIUM accuracy and speed trade-off, average power consumption, 338 33–34 design methodology, 335–336 SystemC-H design environment, 297 heterogeneous, 336–338 Systems in package (SiP), 604, 606, partial dynamic reconfiguration, 610–611 339 reconfigurable processing core, T 333–335 Tagged signal model (TSM), 463 reference locality, 338–339 Task transaction level interface (TTL) MPSoC programming models APIs, abstraction levels, 240 models, 238 HW–SW component integration, 210 primitives, 239 stream processing applications, 239 programming levels, 238 TDL, see Timing definition language multiprocessor system, 331–333 (TDL) platform progrmming models Tilera processor advantages and drawbacks, design methodology, 347 182–184 features, 346 classes, 182 iMesh on-chip network, 346 explicit capture of parallelism, 184 tile64, 345 SiP design process, 606, 610–611 Time-triggered architecture (TTA), 94 SystemC AMS extensions Time-triggered networked control architecture level, 591–592 system cases, 591–592 control performance and network code, 598–599 schedule, 170 methodology-specific support, stand-alone network interface blocks, 595–596 169
Index 737 Timed automata generic description, 416–417 composition, 470–473 input–output specification, continuous/discrete co-simulation 414–415 tools, 535–536 models, digital-clock, 418–419 model checking, exhaustive system under test (SUT), 413–414, verification 420–421 bounded-response property, test case, 416 392–393 tick model, 419–420 Büchi-automaton monitor, 395–396 timed automata with inputs and difference bound matrices (DBMs), outputs (TAIO), 412–413 395 tioco framework, 415 discrete state-transition system, testing, 411–412 393 timing definition language (TDL), properties type, 391–392 474–475 region graph abstraction, 393 Timed automata with inputs and state-explosion, 394 outputs (TAIO), 412–413 time-abstract quotient, 394–395 Timed computation tree logic timed Büchi automata (TBA), (TCTL), 99 395–396 Timed data flow (TDF), 588–591 zone graph, 395 TimeProgressCS_TA method, model-based design, 383–384 471–472 modeling Timing definition language (TDL) Alur–Dill model, 387–388 bind/createnew/delete, 476 clock constraints, 388 execution trace, 479, 481 discrete- vs. dense-time debate, 388 Giotto system, 474–475 finite-state automaton, 386 GReAT transformation, 477–478, operational semantics, 386–387 479 rendez-vous type, 388–389 logical execution time (LET), 474 timed and discrete transitions, 387 MetaGME metamodels, 475 timed automaton (TA), 386 model, 479–480 timing constraints, 386 pseudo-code, 479–480 untimed models, 389 timed automaton (TA), 476–477 operational semantics, 469–470 transformation steps, 476 overview, 466–467 TinyGALS, 241 partial verification Transaction-level modeling (TLM) exhaustive verification tools, 405 abstraction levels, 32 randomized exploration, 406–408 accuracy and speed trade-off simulations, 405 communication refinement, 33–34 state-explosion, 404–405 computation refinement, 34 time-scalability properties, TrueTime 405–406 advantages, 148 semantic unit abstract data model, closed-loop control performance, 467–469 147 TASU modeling language, 473–474 co-simulation tools, 149 TDL modeling language, 475–481 constant bandwidth server (CBS) test generation experiments, 157–159 analog-clock, 417–418 implementation, 156–157 assumptions, 414 updating rules, 156 digital-clock, 417, 419–420 feedback control, 146
738 Index kernel block features object management group (OMG), discrete PI-controller, 154 618–619 initialization script and code RuneII , 618–619 functions, 153 UMTS, see Universal mobile scheduling algorithms, 153 telecommunications system library, 147 Universal mobile telecommunications limitations and extensions system (UMTS) execution times, 171–172 architectural modeling higher-layer protocols, 173 architecture models, 304–306 simulation platform, 173 operating system (OS) scheduling single-core assumption, 170–171 policies, 304 single-thread execution, 172–173 functional modeling mobile robots in sensor networks illustration, 302 bus communication, 164 mechanisms, 302–303 complete model, 165–167 medium access control (MAC), 301 evaluation, 167–168 radio link control (RLC), 301 hardware models, 161–163 mapped system, 306 physical scenario, 161 results radio communication, 164–165 estimated execution time simulation model, 160–161 vs. utilization, 306–309 software components, 160 event analysis, 311–312 network block features first-come-first-serve (FCFS) types and uses, 155 scheduling, 309 wireless networks, 155–156 METRO II simulation phases, network simulators, 148–149 310–311 models, 306 ns-2 discrete-event simulator, 148 priority-based scheduling, 308 pure scheduling simulator, 148 round-robin scheduling, 306 sampled control theory, 146 runtime analysis, 310–311 SimEvents R 2 toolbox, 149 UpdateTimeGuardTA method, 470 Simics system, 149 UPPAAL simulation, 146 advantages, 539–540 time-triggered networked control attributes, 100 system framework model control performance and network abstract task and resource models, schedule, 170 102–103 stand-alone network interface data structures, 103–104 blocks, 169 resource template, 107–109 timing and execution models task template and graphs, implementation, 150 104–107 kernel simulators, 151–152 instantiation network simulators, 152 schedulability problem, TTA, see Time-triggered architecture 114–115 TTL, see Task transaction level interface schedulability query, 113 modeling language U features and stopwatches, 99 UML/XML implementation timed computation tree logic AMS/MT IP blocks, 618–620, 622 (TCTL), 99 class diagram, 620–621 train-gate model, 96–98
Index 739 MoVES analysis framework interface, 711 operating models, 123 output circuitry, 706–708, 709, 710, support, 135–136 711, 712, 713, 714 real-time model checking, 94 application, 702–704 resources, 101–102 distributed architecture, 698–700 single-processor systems, 94 gyroscope, 711, 713 task dependencies, 100–101 microelectromechanical systems time-triggered architecture (TTA), 94 (MEMS), 697–698 Upper event-arrival function, η+ , 61 design methodology, 700–702 models, 698 V simulation Variability characterization curves and validation, 716, 717 (VCCs) gyroscope, 715–717 arrival and service curves, 13–14 IBIS drivers, 714–715 compact representation, 19–22 Virtex 4 FX 100 device, 372–373, 374 Verilog hardware description language (VHDL), 623 X VHDL-AMS Xilinx MPMC, 367 accelerometer description, 704–706 Z IBIS drivers, 708, 710–711, 714 Zero-crossing callback function, 150