Pulse-width modulation strategy for common mode voltage elimination in three-level neutral point clamped inverters with reduced common mode voltage spikes

This paper presents a pulse-width modulation strategy for common mode voltage elimination in the three-level neutral point clamped (NPC) inverter with reduced common mode voltage spikes. The strategy utilizes the three zero common mode voltage vectors in the space vector diagram and is implemented by using a carrier-based pulse-width modulation (PWM) technique.