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Thiết kế mạch bằng VHDL

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VDHL là Ngôn ngữ mô tả phần cứng cho các mạch tích hợp có tốc độ cao, là 1 loại Ngôn ngữ mô tả phần cứng được phát triển dùng cho chương trình VHSIC của bộ quốc phòng Mỹ. Mục tiêu của việc phát triển VHDL là có được Ngôn ngữ mô phỏng phần cứng tiêu chuẩn và thống nhất cho phép thử nghiệm các hệ thống nhanh hơn cũng như cho phép dễ dàng đưa các hệ thống đó vào ứng dụng trong thực tế...

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Nội dung Text: Thiết kế mạch bằng VHDL

  1. M M 6.1. PROCESS ---------------------------------------------------------------------------------------------------------------------- 71 6.2. S Ê VARIABLES. -------------------------------------------------------------------------------------------------------- 72 MC C 6.3. IF. ------------------------------------------------------------------------------------------------------------------------------- 73 6.4. WAIT. -------------------------------------------------------------------------------------------------------------------------- 76 6.5. CASE. --------------------------------------------------------------------------------------------------------------------------- 79 L Ê K ------------------------------------------------------------------------------------------------------------------- 3 6.6. LOOP. -------------------------------------------------------------------------------------------------------------------------- 84 6.7. BAD CLOCKING. ----------------------------------------------------------------------------------------------------------------- 91 1.1. GI T HDL ------------------------------------------------------------------------------------------------------------ 3 V 6.8. S H E----------------------------------------------------------------------- 94 . 1.2. GI ( ) THI VHDL. ------------------------------------------------------ 4 THI 1.2.1 H H D HH E H A ----------------------------------------------------------- 4 L Ê VARIABLE ---------------------------------------------------------------------------------------------------- 97 1.2.2 Quy trinh thi k E H A -------------------------------------------------------------------------------- 5 7.1. CONSTANT. ------------------------------------------------------------------------------------------------------------------- 97 1.2.3. H A -------------------------------------------------------------------------------------------------------------- 6 7.2. SIGNAL. ------------------------------------------------------------------------------------------------------------------------ 97 1.2.4. Chuy H A ------------------------------------------------------------------------------------------ 6 7.3. VARIABLE --------------------------------------------------------------------------------------------------------------------- 99 L D A--------------------------------------------------------------------------------------------------------------- 9 7.4. SU . ---------------------------------------------------------------------------------------------------------------- 107 2.1. C VHDL . ----------------------------------------------------------------------------------------------------------- 9 L HÊ ------------------------------------------------------------------------------------------------------- 119 2.2. K DLIBRARY. --------------------------------------------------------------------------------------------------------------------- 9 8.1. GI .-------------------------------------------------------------------------------------------------------------------- 119 2.3. ENTITY (TH ). -------------------------------------------------------------------------------------------------------------------11 8.2. THI 1 (THI H MAY MOORE). ----------------------------------------------------------- 121 2.4. ARCHITECTURE ( CS ). ------------------------------------------------------------------------------------------------------12 D D 8.3. THI 2. -------------------------------------------------------------------------------------------------------------- 129 2.5. C . -------------------------------------------------------------------------------------------------------------17 8.4. KI D:T ONEHOT. ------------------------------------------------------------------------------- 143 EA Ê L GÊ K ---------------------------------------------------------------------------------------------------------------21 L Ê ------------------------------------------------------------------------------------------ 145 3.1. C . -------------------------------------------------------------------------------------------------21 T 9.1. BARREL SHIFTER. ------------------------------------------------------------------------------------------------------------- 145 3.2. C A. ---------------------------------------------------------------------------------24 9.2. B ÊÊ Đ S . --------------------------------------------------------------------------------------- 148 3.3. C D (SUBTYPES). -----------------------------------------------------------------------------------------------------------25 D S 9.3. B CARRY R E CARRY LOOK AHEAD. ---------------------------------------------------------------- 152 3.4. M (ARRAYS). ---------------------------------------------------------------------------------------------------------------26 E 9.4. B . ---------------------------------------------------------------------------------------------------- 156 3.5. M ( PORT ARRAY). --------------------------------------------------------------------------------------------------29 SS 9.5. BT G. --------------------------------------------------------------------------------------------- 161 3.6. KI (RECORDS). ------------------------------------------------------------------------------------------------------31 9.6. B U I E--------------------------------------------------------------------------------------------------- 166 . 3.7. KI S ( SIGNED AND UNSIGNED). -----------------------------------------------------------31 ĐS 9.7. B U E----------------------------------------------------------------------------------- 169 . 3.8. CHUY . -----------------------------------------------------------------------------------------------------------33 ÊDÊ D 9.8. T 7 THANH. ----------------------------------------------------------------------------------------------- 170 3.9. TĐ .-------------------------------------------------------------------------------------------------------------------------------35 9.9. BE . ------------------------------------------------------------------------------------------------------------ 175 3.10. C . ----------------------------------------------------------------------------------------------------------------------------35 9.10. THI . ------------------------------------------------------------------------------------------------------------- 178 L Ê THU ---------------------------------------------------------------------------------------------43 L Ê ------------------------------------------------------------- 185 4.1. TD . ------------------------------------------------------------------------------------------------------------------------43 10.1 T QUAN PH M H TRPC PLD ---------------------------------------------------------------- 185 4.1.1. H H -----------------------------------------------------------------------------------------------------------------43 10.1.1. PALASM 2 (PAL ASSEMBLER) --------------------------------------------------------------------------------------- 185 4.1.2. H ------------------------------------------------------------------------------------------------------------43 10.1.2. AMAZE -------------------------------------------------------------------------------------------------------------------- 185 H H T -----------------------------------------------------------------------------------------------------------44 10.1.3. PLAN ( Programmable Logic Analysis) --------------------------------------------------------------------------- 185 4 H H ------------------------------------------------------------------------------------------------------------44 10.1.4. HELD (Harris Enhanced Language for Programmable Logic)---------------------------------------------- 185 O H -----------------------------------------------------------------------------------------------------------------44 10.1.5. PLPL (Programmable Logic Programming Language) ------------------------------------------------------- 185 4.2. THU .---------------------------------------------------------------------------------------------------------------------44 10.1.6. APEEL (Assembler for Programmable Electrically Erasable Logic) --------------------------------------- 185 4.2.1. ThuU H ----------------------------------------------------------------------------------------------------------44 10.1.7. IPLDS II (Intel Programmable Logic Devolopment System II) ---------------------------------------------- 186 4.2.2. ThuU H H ---------------------------------------------------------------------------------------------------------45 10.1.8. CUPL ( Universal Compiler for Programmable Logic ) ------------------------------------------------------- 186 4.3. THU . ---------------------------------------------------------------------------46 NGH 10.1.9. ABEL (Advanced Boolean Expression Language)-------------------------------------------------------------- 186 4.4. CH . ----------------------------------------------------------------------------------------------------------------------46 D XX : H -------------------------------------------------------------------------------------- 187 4.5. GENERIC. ----------------------------------------------------------------------------------------------------------------------47 VI M 10.2. S D PH M ISE WEDPACK 9.2 ------------------------------------------------------------------------------- 187 4.6. V . ----------------------------------------------------------------------------------------------------------------------------------48 10.2. HH HD SI H ------------------------------------------------------------ 187 L ÊA NG -----------------------------------------------------------------------------------------------------------53 10.2.2. T U Ì -------------------------------------------------------------------------------------------------- 189 10.2.3. T U HI ------------------------------------------------------------------------ 195 5.1. SD Ê . -------------------------------------------------------------------------------------------------------53 D 10.2.4. Thi H H H ------------------------------------------------------------------------------------- 199 5.1.1. M I -----------------------------------------------------------------------------------------------53 10.3. GI THI PH M MODELSIM ISE WEB PACK------------------------------------------------------------------- 204 O HH H -------------------------------------------------------------------------------------------53 5.2. S . ---------------------------------------------------------------------------------------------------------54 D 5.3. M T HEN. --------------------------------------------------------------------------------------------------------------------55 W 5.4. GENERATE. --------------------------------------------------------------------------------------------------------------------64 5.5. BLOCK. -------------------------------------------------------------------------------------------------------------------------66 5.5.1. Simple BLOCK ----------------------------------------------------------------------------------------------------------------66 5.1.2. Guarded BLOCK -------------------------------------------------------------------------------------------------------------68 L ÊA ---------------------------------------------------------------------------------------------------------------71 Thik k Thik k Trang 1 / 208 Trang 2 / 208
  2. Y Y nhau tuê õ _ ã ã à GI ã 1.1. Gi thi v â â ù Th _ú _õ ãù _ õ _ ú õã _ ã_ _ú ã í (Very High ú _ ú õã _ c Speed Itergrated Circuit) c _ ù __ _ _ d ã_ _ ù bú _ú ã _ú nghi _ íè ã ã ã _ â õí â Th Texas Instruments b ã _ úã _ ã ù __ õ chu ã ã ã ã ùã - _úã ã ú_ú ã m _ _ _ ãã ã chu -1076-1987). è _ _ ã _ ú_ ã ãú ã _ ãã ã c _ ã ùê_ â ú íí â à íí Th í _ _ú í _ ã _ ã th ù ã_ _ ù ã _ _ _ _ ng d _ ã_ í ú _ è õ ã thi ù Th _ ò 1.2. Gi ã ú _ VHDL. ã ú ù è chu ò ù _ 1.2.1 Hi â ú ì ì í Th ã __ ices PLD) (bao g _ kí: õ ã b - Field Programmable Gate í í è õ xu _ VHDL m _õ ã ã ã _ ã _ú ma tr th ã õ_ í_õ õ ã ã ù Th ã õ _ú _ ã ú _õ VHDL thi Thik k Thik k Page 3 / 208 Trang 4 / 208
  3. Y Y ò 1.2.2 Quy trinh thi 1.2.3. ã _ õ _õ tõ _ _ Active HDL: ph ã vi mõ ho _õ ã ãõ Vi : _ ã _õ ã ã ã õ _ :B ã _ G _õ ph HDL. ã ã *.vhd ã _ú ã _ chip CPLD/FPGA c chips). _ ò 1.2.4. Chuy ã ãã _ú ã M õ ìùù ã 2. ã cin cout õã _ã õ õ ú nh é íí 1. ãõ tõ : í _ _ 1: dich s t ã ã : t netlist õ _ ãõ th ã _ ã _ xú õ 3. B â ùù ã ãõ ã __ : cin _ ãõ õ õ _ õ cout ã s=a b = a.b + a.cin + b.cin Bit s out cho ASIC. Thik k Thik k d VHDL Trang 5 / 208 Trang 6 / 208
  4. Y Y ta vi ãõ _ ã T out ã ã N m o ú cout thoú_ (cout = a.b + a.cin + b.cin). k cho ã N m ds _ õ d Bù _ _õ ã t_ ã _ _ ã ù è _ ã nh ã ù õ th ã _ ú ãõ í ã _õ ãã c í íùù 4. T_ _õv ã õ ã í ã _ ú _õ ã ã ã _ ã thu ã _s õ _õ 6 . Kí â ò ùù íí ì à 5. Thik k Thik k d VHDL Trang 7 / 208 Trang 8 / 208
  5. Y Y 2: C 2: C à C í _ú íú ú ãõ a VHDL: LIBRARY, ENTITY ARCHITECTURE. à_ àô ã _ _ M _ ùú ã ã â ù à 2. 1. trong thi ú _õ EN s) c _ _ úõ _ ã ARCHITECTURE: Ch _ ã ã _ M ã ã ã ã õ ã ãã ã vi _ hù Library ã â ù 2. 2. __ ã LIBRARY library_name; LIBRARY ieee; -- D USE library_name.package_name.package_parts; ô USE ieee.std_logic_1164.all;-- kt c ã ieee.std_logic_1164 (from the ieee library), -- hoì ã LIBRARY std; standard (from the std library), and ó é USE std.standard.all; -- (-- work (work library). LIBRARY work; USE work.all; _ã std work úã ieee Thik k Thik k Page 9 / 208 Trang 10 / 208
  6. Y Y 2: C 2: C Mã ã _ ù_ ùê std_logic_1164 c vi ieee cho bi _ ã_ _ std , c _ ã i/o text d ã õ í í _ file * ph ENTITY nand_gate IS PORT (a, b : IN BIT; Th ieee ch x : OUT BIT); std_logic_1164: ã GIC (8 m 9m ã_ END nand_gate; h std_logic_arith: ã ú è _ ã _ _ ã ã conv_integer(p),conv_unsigned(p, b), conv_signed(p, b), conv_std_logic_vector(p, b) _ _ std_logic_signed: ch ãã íù 2. 4. Cõ = = 2. 3. _ _ std_logic_signed: ch 2.4. ARCHITECTURE ( c ãã _ _ úõ _ ã _õ _ 2.3. Entity (th ch _ _ú _ã õ M ARCHITECTURE architecture_name OF entity_name IS ENTITY entity_name IS PORT ( [declarations] port_name: signal_mode signal_type; BEGIN port_name: signal_mode signal_type; (code) ...); END architecture_name; END entity_name; ù _ ù í Ch ã _ ã _ -t ù _ d õ úã tro õ li ARCHITECTURE myarch OF nand_gate IS Ki BEGIN x
  7. Y Y 2: C 2: C Z(3)
  8. Y Y 2: C 2: C 1: 2: Architecture arc_mach_cong of mach_cong is Component Xor Port( X,Y : in bit ; Z, T : out bit); End component; 2. 5 er RS Component And Port(L,M :input ;N,P : out bit ); ENTITY rsff IS PORT( r : IN std_logic; End component; s : IN std_logic; Begin q : OUT std_logic; G1 : Xor port map (A,B,Sum); qb : OUT std_logic); G2 : And port map (A, B, C); END rsff; End arc_mach_cong; ARCHITECTURE kien_truc OF rsff IS COMPONENT nand -- GENERIC(delay : time); PORT(a : IN std_logic; _ _ b : IN std_logic; c : OUT std_logic); END COMPONENT; Entity adder is BEGIN Port (A,B,Ci : bit ì é u1: nand -- S, Cout : bit); ó GENERIC MAP(5 ns) -- End adder; values é PORT MAP(s, qb, q); -- b Architecture arc_mixed of adder is ê é u2: nand -- thi Component Xor2 GENERIC MAP(5 ns) Port( P1, P2 : in bit; PORT MAP(q, r, qb); PZ : out bit); END kien_truc; End compenent; Signal S1 :bit; Thik k Thik k d VHDL Trang 15 / 208 Trang 16 / 208
  9. Y Y 2: C 2: C 1 --------------------------------------- Begin 2 LIBRARY ieee; X1 : Xor2 port map(A,B,S1); 3 USE ieee.std_logic_1164.all; Process (A,B,Cin) 4 --------------------------------------- 5 ENTITY dff IS Variable T1,T2,T3 : bit; 6 PORT ( d, clk, rst: IN STD_LOGIC; Begin 7 q: OUT STD_LOGIC); T1 := A and B; 8 END dff; 9 --------------------------------------- T2 := B and Cin ; 10 ARCHITECTURE behavior OF dff IS T3 := A and Cin; 11 BEGIN Cout := T1 or T2 or T3 ; 12 PROCESS (rst, clk) 13 BEGIN End process; 14 IF (rst='1') THEN End arc_mixed ; 15 q
  10. Y Y 2: C 2: C ã _ ú_ _õ ph K _ ã í t DFF k Mõ ã ú ã ã _ ã _ _ ã_ h_ ã hi 2 . 9 . Kí â ò 2. 8. DFF kí õ == --------------------------------------- ENTITY example IS PORT ( a, b, clk: IN BIT; q: OUT BIT); END example; --------------------------------------- ARCHITECTURE example OF example IS SIGNAL temp : BIT; BEGIN temp
  11. Y Y 3: K I 3: K I & à … KI & && & _ _ ú ã _ ã _ ãã í ùú íú ã _ú ki ãã H À 3.1. ã ã VHDL bao g _ _ _ ã éã ã & ù ù & í ã é m m d _ù m m é _ : tr - SIGNAL x: STD_LOGIC; é _ = " -- STD_ULOGIC. ,: thu SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001"; é hc _ = = = -- -bit, v _ _ ã conv_integer(p), conv_unsigned(p, b), _ -- _ _ -- r _ : Ch _ ã ã _ _ ã _ & H h std_logic d õ ã â ì â T : giú ã ú std_logic bù êã ã _ _ Th _ ã ã ã ú ú SIGNAL x: BIT; Bâ ô â 1. H ô_ ó -- SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- SIGNAL w: BIT_VECTOR (0 TO 7); ú -- ã ã _ ã_ D ã Thik k Thik k Page 21 / 208 Trang 22 / 208
  12. Y Y 4: 3: K I _ SIGNAL a: BIT; STD_ULOGIC( STD_ULOGIC_VECTOR): h hu & SIGNAL b: BIT_VECTOR(7 DOWNTO 0); _ú _ _ SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0); ã SIGNAL e: INTEGER RANGE 0 TO 255; ... ã INTEGER: s - ) ó a
  13. Y Y 4: 3: K I ô ô ó TYPE bit_vector IS ARRAY (NATURAL RANGE ) OF BIT; liô ó ô -- SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1'; _ ó í -- hã SIGNAL a: BIT; -- NATURAL RANGE , on the other hand, indicates that the SIGNAL b: STD_LOGIC; only SIGNAL c: my_logic; -- restriction is that the range must fall within the NATURAL ... -- range. ô ó ó b
  14. Y Y 4: 3: K I ã ã ãù ã _ VARIABLE h d ã ã ã ã ã ã ã ã _ __ ú ... :="0001"; -- for 1D array TYPE type_name IS ARRAY (specification) OF data_type; ... :=('0','0','0','1') -- for 1D array óã_ ó ... :=(('0','1','1','1'), ('1','1','1','0')); -- for 1Dx1D or- SIGNAL signal_name: type_name [:= initial_value]; - 2D array _ ã è _ â _ õ CONSTANT ho ã ã é : sau: _ __ú _ TYPE row IS ARRAY (7 DOWNTO 0)OF STD_LOGIC; ã __ ú _ _ú ng (row) -- 1D array _ (matrix) í _ _ ch TYPE array1 IS ARRAY (0 TO 3) OF row; _ & ã ã ã_ ú s -- 1Dx1D array TYPE array2 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0); TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array -- 1Dx1D TYPE matrix IS ARRAY (0 TO 3) OF row; -- 1Dx1D array TYPE array3 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; SIGNAL x: matrix; -- 1Dx1D signal -- 2D array SIGNAL x: row; ã _ú ã SIGNAL y: array1; SIGNAL v: array2; TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL w: array3; --------- --------------- Mú ã ã -- lô ãõ ó -- b TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; ô -- 2D array -- (x,y,v,w). ã mâ * Kh ì ì x(0)
  15. Y Y 4: 3: K I ã _ ú ã -- 1 cì ì _ x(2)
  16. Y Y 4: 3: K I í _ à ã && ------- Package: ------------------------------- & bi -3 LIBRARY ieee; USE ieee.std_logic_1164.all; std_logic_arith c ieee, phú ã ù ù ---------------------------- ú ã é PACKAGE my_data_types IS ù _ õ STD_LOGIC_VE CONSTANT b: INTEGER := 7; ã TYPE vector_array IS ARRAY (NATURAL RANGE ) OF STD_LOGIC_VECTOR(b DOWNTO 0); ã END my_data_types; ---------------------------------------------- LIBRARY ieee; ô 3.6. Ki USE ieee.std_logic_1164.all; Bú í _ú ã_ ã é USE ieee.std_logic_arith.all; -- li ... SIGNAL a: IN SIGNED (7 DOWNTO 0); TYPE birthday IS RECORD SIGNAL b: IN SIGNED (7 DOWNTO 0); day: INTEGER RANGE 1 TO 31; SIGNAL x: OUT SIGNED (7 DOWNTO 0); month: month_name; ... END RECORD; ô _ ú v
  17. Y Y 4: 3: K I _ ã ã _ ô w
  18. Y Y 4: 3: K I , SIGNAL z: STD_LOGIC_VECTOR (x'HIGH DOWNTO 0); -- 1D signal í úã _ ú SIGNAL w1: mem1; -- 2D signal SIGNAL w2: mem2; -- 1Dx1D signal Bâ 2 . Tõ SIGNAL w3: mem3; -- 1Dx1D signal -------- Legal scalar assignments: --------------------- x(2)
  19. Y Y 4: 3: K I w1(2,5)
  20. Y Y 4: 3: K I x
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