Verilog Tidbits

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[ Team LiB ] Origins of Verilog HDL Verilog HDL originated around 1983 at Gateway Design Automation, which was then located in Acton, Massachusetts. The language that most influenced Verilog HDL was HILO-2, which was developed at Brunel University in England under contract

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[ Team LiB ] Origins of Verilog HDL Verilog HDL originated around 1983 at Gateway Design Automation, which was then located in Acton, Massachusetts. The language that most influenced Verilog HDL was HILO-2, which was developed at Brunel University in England under contract to produce a test generation system for the British Ministry of Defense. HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification simulation, timing analysis, fault simulation, and test generation. Gateway Design Automation was privately held at that time and was headed by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was introduced into the EDA market in 1985 as a simulator product. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA, in 1989. Verilog HDL was opened to the public by Cadence Design Systems in 1990. Open Verilog Internation(OVI) was formed to standardize and promote Verilog HDL and related design automation products. In 1992, the Board of Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993, the first IEEE Working Group was formed and, after 18 months of focused efforts, Verilog became the IEEE Standard 1364-1995. After the standardization process was complete, the 1364 Working Group started looking for feedback from 1364 users worldwide so that the standard could be enhanced and modified accordingly. This led to a five-year effort to create a much better Verilog standard IEEE 1364- 2001. [ Team LiB ] [ Team LiB ] Interpreted, Compiled, Native Compiled Simulators Verilog simulators come in three flavors, based on the way they perform the simulation. Interpreted simulators read in the Verilog HDL design, create data structures in memory, and run the simulation interpretively. A compile is performed each time the simulation is run, but the compile is usually very fast. An example of an interpreted simulator is Cadence Verilog-XL simulator. Compiled code simulators read in the Verilog HDL design and convert it to equivalent C code (or some other programming language). The C code is then compiled by a standard C compiler to get the binary executable. The binary is executed to run the simulation. Compile time is
usually long for compiled code simulators, but, in general, the execution speed is faster compared to interpreted simulators. An example of compiled code simulator is Synopsys VCS simulator. Native compiled code simulators read in the Verilog HDL design and convert it directly to binary code for a specific machine platform. The compilation is optimized and tuned separately for each machine platform. Of course, that means that a native compiled code simulator for a Sun workstation will not run on an HP workstation, and vice versa. Because of fine tuning, native compiled code simulators can yield significant performance benefits. An example of a native compiled code simulator is Cadence Verilog-NC simulator. [ Team LiB ] [ Team LiB ] Event-Driven Simulation, Oblivious Simulation Verilog simulators typically use an event-driven or an oblivious simulation algorithm. An event- driven algorithm processes elements in the design only when signals at the inputs of these elements change. Intelligent scheduling is required to process elements. Oblivious algorithms process all elements in the design, irrespective of changes in signals. Little or no scheduling is required to process elements. [ Team LiB ] [ Team LiB ] Cycle-Based Simulation Cycle-based simulation is useful for synchronous designs where operations happen only at active clock edges. Cycle simulators work on a cycle-by-cycle basis. Timing information between two clock edges is lost. Significant performance advantages can be obtained by using cycle simulation. [ Team LiB ] [ Team LiB ] Fault Simulation Fault simulation is used to deliberately insert stuck-at or bridging faults in the reference circuit. Then, a test pattern is applied and the outputs of the faulty circuit and the reference circuit are compared. The fault is said to be detected if the outputs mismatch. A set of test patterns is developed for testing the circuit. [ Team LiB ] [ Team LiB ] General Verilog Web sites The following sites provide interesting information related to Verilog HDL.
1. Verilog— http://www.verilog.com 2. Cadence— http://www.cadence.com/ 3. EE Times— http://www.eetimes.com 4. Synopsys— http://www.synopsys.com/ 5. DVCon (Conference for HDL and HVL Users)— http://www.dvcon.org 6. Verification Guild— http://www.janick.bergeron.com/guild/default.htm 7. Deep Chip— http://www.deepchip.com [ Team LiB ] [ Team LiB ] High-Level Verification Languages 1. Information on e is available at http://www.verisity.com 2. Information on Vera is available at http://www.open-vera.com 3. Information on SuperLog is available at http://www.synopsys.com 4. Information on SystemVerilog is available at http://www.accellera.org [ Team LiB ] [ Team LiB ] Simulation Tools 1. Information on Verilog-XL and Verilog-NC is available at http://www.cadence.com 2. Information on VCS is available at http://www.synopsys.com [ Team LiB ] [ Team LiB ] Hardware Acceleration Tools Information on hardware acceleration tools is available at the Web sites of the following companies: 1. http://www.cadence.com 2. http://www.aptix.com 3. http://www.mentorg.com 4. http://www.axiscorp.com 5. http://www.tharas.com [ Team LiB ] [ Team LiB ]
In-Circuit Emulation Tools Information on in-circuit emulation tools is available at the Web sites of the following companies. 1. http://www.cadence.com 2. http://www.mentorg.com [ Team LiB ] [ Team LiB ] Coverage Tools Information on coverage tools is available at the Web sites of the following companies: 1. http://www.verisity.com 2. http://www.synopsys.com [ Team LiB ] [ Team LiB ] Assertion Checking Tools Information on assertion checking tools is available at the Web sites of the following companies: 1. Information on e is available at http://www.verisity.com 2. Information on Vera is available at http://www.open-vera.com 3. Information on SystemVerilog is available at http://www.accellera.org 4. http://www.0-in.com 5. http://www.verplex.com 6. Information on Open Verification Library is available at http://www.accellera.org [ Team LiB ] [ Team LiB ] Equivalence Checking Tools 1. Information on equivalence checking tools is available at http://www.verplex.com 2. Information on equivalence checking tools is available at http://www.synopsys.com [ Team LiB ] [ Team LiB ]
Formal Verification Tools Information on formal verification tools is available at the Web sites of the following companies: 1. http://www.verplex.com 2. http://www.realintent.com 3. http://www.synopsys.com 4. http://www.athdl.com 5. http://www.0-in.com [ Team LiB ]