Modules and ports

In this tutorial, you will learn how to setup a ModelSim project, compile your Verilog files, correct compilation errors, and perform design debugging using ModelSim. The example design used within this tutorial is simple Synchronous Serial Port (SSP) that contains both a send and receive module.

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The Verilog HDL supports a hierarchical hardware description structure by allowing modules to be embedded within other modules. Higher level modules create instances of lower level modules and communicate with them through input, output, and bidirectional ports. These module input/output (I/O) ports can be scalar or vector.

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Cisco ATM router interfaces support an MTU between 64 and 17966 bytes. Each interface supports a default maximum packet size. For example, the maximum value is 9288 bytes on both the ATM interface processor (AIP) and network processor module (NP), and 4470 bytes on the PA-A3 and PA-A2 port adapters.

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[ Team LiB ] 4.2 Ports Ports provide the interface by which a module can communicate with its environment. For example, the input/output pins of an IC chip are its ports. The environment can interact with the module only through its ports.

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[ Team LiB ] 4.1 Modules We discussed how a module is a basic building block in Chapter 2, Hierarchical Modeling Concepts. We ignored the internals of modules and concentrated on how modules are defined and instantiated.

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