Verilog constructs

This paper describes a compiler, which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics, of Verilog and performs logic minimization. Busses of up to 32 or 64 bits can be modeled as C integers whereas larger busses are automatically split. We describe the motivation, method and quality of the results.

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Certified that the work contained in the thesis entiled " Verilog-to-C-Compiler: Simulator Generator " by " Anand Vivek Srivastava", has been carried out under my supervision and that this work has not been submitted elsewhere for a degree. This paper describes a compiler, which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics, of Verilog and performs logic minimization.

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Synthesis Design Flow Having understood how basic Verilog constructs are interpreted by the logic synthesis tool, let us now discuss the synthesis design flow

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Examples In this section, we discuss how to build practical digital circuits, using switch-level constructs. 11.2.1 CMOS Nor Gate Though Verilog

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Switch-Modeling Elements Verilog provides various constructs to model switch-level circuits. Digital circuits at MOS-transistor level are described using these elements.[1]

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Examples In order to illustrate the use of behavioral constructs discussed earlier in this chapter, we consider three examples in this section. The first two, 4-to-1 multiplexer and 4-bit counter, are taken from Section

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Timing Controls Various behavioral timing control constructs are available in Verilog. In Verilog, if there are no timing control statements

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Continuous assignment is one of the main constructs used in dataflow modeling. A continuous assignment is always active and the assignment expression is evaluated

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[ Team LiB ] 11.2 Examples In this section, we discuss how to build practical digital circuits, using switch-level constructs. 11.2.1 CMOS Nor Gate Though Verilog has a nor gate primitive, let us design our own nor gate,using CMOS switches.

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[ Team LiB ] 11.1 Switch-Modeling Elements Verilog provides various constructs to model switch-level circuits. Digital circuits at MOS-transistor level are described using these elements.[1] Array of instances can be defined for switches.

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[ Team LiB ] 14.4 Synthesis Design Flow Having understood how basic Verilog constructs are interpreted by the logic synthesis tool, let us now discuss the synthesis design flow from an RTL description to an optimized gate-level description. 14.4.1 RTL to Gates

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[ Team LiB ] 14.3 Verilog HDL Synthesis For the purpose of logic synthesis, designs are currently written in an HDL at a register transfer level (RTL). The term RTL is used for an HDL description style that utilizes a combination of data flow and behavioral constructs.

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[ Team LiB ] 7.3 Timing Controls Various behavioral timing control constructs are available in Verilog. In Verilog, if there are no timing control statements, the simulation time does not advance. Timing controls provide a way to specify the simulation time at which procedural statements will execute

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