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VLSI design
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In this paper, we present a numerical simulation design of a 1:2 power splitter optical circuit with an evenly distributed 50:50 splitting ratio for all three modes simultaneously. The proposed design is based on the SOI material platform with wafers having a silicon layer thickness of 220nm, in accordance with VLSI chip manufacturing technology standards.
9p
vithomson
02-07-2024
0
0
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Part 1 book "Technology computer aided design - Simulation for VLSI MOSFET" includes content: Introduction to technology computer aided design; basic semiconductor and metal oxide semiconductor (MOS) physics; review of numerical methods for technology computer aided design (TCAD), device simulation using ISE-TCAD.
204p
dianmotminh03
17-06-2024
2
0
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Part 2 book "Technology computer aided design - Simulation for VLSI MOSFET" includes content: Device simulation using silvaco ATLAS tool, study of deep Sub-Micron VLSI MOSFETs through TCAD, MOSFET characterization for VLSI circuit simulation, process simulation of a MOSFET using TSUPREM-4 and medici.
241p
dianmotminh03
17-06-2024
1
0
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Part 1 book "Digital integrated circuit design - From VLSI architectures to CMOS fabrication" includes content: Introduction to microelectronics, from algorithms to architectures, functional verification, modelling hardware with VLSI, the case for synchronous design, clocking of synchronous circuits, acquisition of asynchronous data, gate and transistor level design.
484p
dianmotminh01
17-05-2024
4
2
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Part 2 book "Digital integrated circuit design - From VLSI architectures to CMOS fabrication" includes content: Energy efficiency and heat removal, signal integrity, physical design, design verification, VLSI economics and project management, a primer on CMOS technology, outlook.
395p
dianmotminh01
17-05-2024
3
2
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Part 1 book "VLSI architectures for modern error-correcting codes" includes content: Finite field arithmetic, VLSI architecture design fundamentals, root computations for polynomials over finite fields, algebraic soft-decision Reed-Solomon decoder architectures, Reed-Solomon encoder and hard-decision and erasure decoder architectures, interpolation-based Chase and generalized minimum distance decoders.
211p
dianmotminh00
17-04-2024
3
2
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Bài giảng HDL & FPGA - Chương 1: Giới thiệu chung về công nghệ IC khả trình. Chương này cung cấp cho sinh viên những nội dung kiến thức gồm: các bước thiết kế VLSI; các bước thiết kế vật lý; các công nghệ dùng trong thiết kế; công nghệ IC khả trình; ứng dụng của công nghệ IC khả trình;... Mời các bạn cùng tham khảo!
70p
nguyetthuongvophong1010
04-03-2024
10
1
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Lecture Digital systems - Chapter 1a: Design concepts. This lesson provides students with content about: IC density of integration; different types of Integrated circuit chips; standard chips; programmable logic devices; custom chips; structure of a computer; VLSI design flow;...
39p
nguyetthuongvophong1010
04-03-2024
9
1
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Non-binary low-density parity-check (NBLDPC) codes have a better error-correcting performance in comparison with their binary counterparts when the code length is moderate. However, NB-LDPC decoding is high complexity, especially the check node processing. In this paper, a novel check node processing algorithm and corresponding architectures are proposed for the trellis min-max NB-LDPC decoding to reduce the hardware complexity. A layered decoder architecture is implemented for the (2304, 2048) NB-LDPC code over GF(16) based on the proposed algorithm with a 90-nm CMOS technology.
4p
wangziyi_1307
26-04-2022
11
1
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Lecture Design and Implementation of VLSI systems - Lesson 1: The big picture provide students with knowledge about introduction to VLSI systems; history; tour of VLSI Design and Implementation; IC market; design flow;...
280p
linyanjun_2408
23-04-2022
12
2
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Lecture Design and Implementation of VLSI systems - Lesson 4: MOSFET provide students with knowledge about MOSFET; MOS transistor theory; gate-oxide-body sandwich = capacitor; gate capacitance as a function of Vgs; the MOS transistor has three regions of operation;...
46p
linyanjun_2408
23-04-2022
16
2
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Lecture Design and Implementation of VLSI systems - Lesson 2: CMOS logic provide students with knowledge about impact of doping on silicon resistivity; PN-junction regions of operation; nMOS and pMOS transistors; more CMOS gates;...
24p
linyanjun_2408
23-04-2022
15
1
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Lecture Design and Implementation of VLSI systems - Lesson 3: CMOS fabrication provide students with knowledge about CMOS fabrication; fabricating one transistor; wafer preparation; expose N well mask; develop resist; implant N well; remove resist;...
32p
linyanjun_2408
23-04-2022
12
1
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Lecture Design and Implementation of VLSI systems - Lesson 5: Delay provide students with knowledge about introduction and delay definitions; delay estimation; logical effort for delay estimation; how to calculate delay; transistor resistance; switch level RC models;...
92p
linyanjun_2408
23-04-2022
9
1
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Lecture Design and Implementation of VLSI systems - Lesson 6: Performance estimation provide students with knowledge about performance estimation; power in circuit element; source of power dissipation; charging a capacitor; switching waveforms; switching power;...
49p
linyanjun_2408
23-04-2022
15
1
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Bài giảng Thiết kế hệ thống nhúng (Embedded Systems Design) - Chương 2 (Bài 6): Công nghệ IC. Những nội dung chính trong bài này gồm có: Cấu trúc IC, công nghệ IC chức năng chung (VLSI), công nghệ IC chức năng chuyên biệt (ASIC), công nghệ IC có thể lập trình (PLD). Mời các bạn cùng tham khảo.
17p
lovebychance03
13-07-2021
23
4
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In this paper, we introduce a compact Polar-code-based VLC receivers. in which flicker mitigation of the system can be guaranteed even without RLL codes. In particular, we utilized the centralized bit-probability distribution of a pre-scrambler and a Polar encoder to create a non-RLL flicker mitigation solution. At the receiver, a 3-bit soft-decision filter was implemented to analyze signals received from the VLC channel to extract log-likelihood ratio (LLR) values and feed them to the Polar decoder.
15p
trinhthamhodang9
10-12-2020
16
0
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Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model.
6p
kequaidan1
16-11-2019
25
0
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Systolic architectures are designed by using linear mapping techniques on regular dependence graphs (DG). Systolic architectures have a space-time representation where each node is mapped to a certain processing element (PE) and is scheduled at a particular time instance. Chapter 7 will discuss the systolic architecture design, inviting you refer.
27p
shiwo_ding6
31-05-2019
38
1
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The main contents of this chapter include all of the following: Cook-toom algorithm and modified cook-toom algorithm, winograd algorithm and modified winograd algorithm, iterated convolution, cyclic convolution, design of fast convolution algorithm by inspection.
50p
shiwo_ding6
31-05-2019
40
1
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