Kỹ thuật viễn thông_Lab 6

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I/ OBJECTIVES After completing this experiment, you should be able to: - Implement the decade counters, dual decade counters and presettable 4-bit binary up/down counter - Design programmable frequency division. - Understand the operations of some IC counters. II/ COMPONENTS REQUIRED 1. Main board and sub board of Digital Logic System Kit. 2. IC 74LS90 : Decade Counters 3. IC 74LS193: Presettable 4-bit binary up/down counter 4. IC 74LS390: Dual 4-Bit Decade Counter

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INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE) DIGITAL LOGIC SYSTEMS LABORATORY Lab 6 COUNTER IC Full name:................................................................... Student Number:...................................................... Class:............................................................................. Date:.............................................................................. DIGITAL LOGIC SYSTEMS Page 1 of 10
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE) I/ OBJECTIVES After completing this experiment, you should be able to:  Implement the decade counters, dual decade counters and presettable 4-bit binary up/down counter  Design programmable frequency division.  Understand the operations of some IC counters. II/ COMPONENTS REQUIRED 1. Main board and sub board of Digital Logic System Kit. 2. IC 74LS90 : Decade Counters 3. IC 74LS193: Presettable 4-bit binary up/down counter 4. IC 74LS390: Dual 4-Bit Decade Counter III/ INTRODUCTION 1. Decade and binary counter 74LS90  Implement given circuit and get the results  Use an extra IC 74LS00 and wire them as a MOD-6 counter 2. Dual 4-bit decade counters 74LS390  Wire the 74LS390 as a MOD-100 counter  Wire the 74LS390 as a MOD-60 counter. 3. Presettable 4-bit binary up/down counter  Describe the function of each input and output.  Variable MOD number using the 74193 (Up and Down counter) IV/ PRE-LAB - Pre-lab includes reading the lab assignment in advance, answering the questions or doing the calculations, and if necessary reviewing the material in the textbook. All pre- lab preparation must be recorded and dated in the lab sheet prior do doing the lab. The lab instructor will check your pre-lab write-up and sign your pre-lab sheet. - Answering all the questions, fulfill the truth table and draw circuit or logic diagram (in figures 3, 5, 6, 9, 10, 11) on this experiment before doing the lab. - If you don’t prepare the pre-lab, you will not allowed to experiment. IV/ EXPERIMENT 1. COMMON ANODE 7-SEGMENT LED & DECODER IC 74LS47 SW8 -SW11 6 1 3 2 D a 1 2 1 C b 1 1 7 B c 1 0 A d 9 e 1 5 ( A (a,b,c,d,e,f,g)) LED A f SW 12 3 LT g 1 4 ,B ,C ,D ,E ,F ,G L E D A 5 SW 13 4 R BI SW 14 B I/R B O 74LS47 Figure 1 – IC7447 and 7-segment - LED DIGITAL LOGIC SYSTEMS Page 2 of 10
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE)  The pins a, b, c, d, e, f, g of IC 7447 are connected to a, b, c, d, e, f, g of 7-segment led display shown in figure 1  The data inputs D, C, B, A are connected to switches  The control inputs LT, RBI, BI/RBO are connected to switches and they are in the appropriate states to make the circuit operating  Fulfill the truth table of IC7447 in Table 1 Inputs Outputs Control inputs Data inputs Display LT RBI RBO D C B A a b c d e f g 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 0 1 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 X X X X X 0 1 X X X X X X 0 X X X X Table 1 – True table of IC7447  What is the function of the pins: Lamp-Test (LT), Ripple-Blanking Input (RBI), Blanking Input or Ripple Blanking Output (BI/RBO): Lamp Test (LT): .................................................................................................................... ............................................................................................................................................. Ripple-Blanking Input (RBI): ............................................................................................... ............................................................................................................................................. Blanking Input/Ripple Blanking Output (BI/RBO): ............................................................. ............................................................................................................................................. 2. Decade counter 74LS90 DIGITAL LOGIC SYSTEMS Page 3 of 10
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE) Figure 2: IC 74LS90 IC 74LS90 contains a divide-by-two counter and a divide-by-five counter. Each counter can be used separately or tied together (QA to input B) to form BCD counter. 74LS90 have 2 Master Reset inputs (R0(1), R0(2)) and 2 Master Set inputs (R9(1), R9(2)). a.Implement BCD counter Imlement BCD counter using 74LS90. • Connect Clock signal to CLKA • Connect QA to CLKB • Connect R01, R02, R91, R92 to switches for controlling operations • Connect outputs (QA, QB, QC, QD) to BCD to 7-segment display block 14 12 C LO C K C LKA Q A 1 9 C LKB Q B 8 2 Q C 11 3 R 0 1 Q D 6 R 0 2 BCD TO 7-SEGMENT DISPLAY 7 R 9 1 SW 1,2,3,4 R 9 2 74LS90 Figure 3: BCD counter b. Use an extra IC 74LS00 and wire them as a MOD-7 counter (counting from 0 to 6).  Draw the circuit appropriately in figure 4.  Implement the circuit and observe the results on 7-segment-led. DIGITAL LOGIC SYSTEMS Page 4 of 10
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE) Figure 4 – Mod 7 counter using 74LS90 and 74LS00  Show the way to implement: ............................................................................................................................................ ............................................................................................................................................ ............................................................................................................................................ ..................................................................................... 3. IC 74LS390: DUAL 4-BIT DECADE COUNTER Figure 5 – Logic diagram of 74LS390  IC 74LS390 includes 2 decimal counters as figure 5  CLR: Clear (high level active)  QA, QB, QC and QD: outputs of the MOD-10 counter a. Wire the 74LS390 as a MOD-100 counter  Implement the circuit shown in logic diagram of Figure 6  The outputs QA, QB, QC and QD are connected to BCD TO 7-SEGMENT DISPLAY  The CLR inputs are connected to switches to control the circuit operation. DIGITAL LOGIC SYSTEMS Page 5 of 10
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE) U 1A C LO C K 1 3 4 C KA Q A 5 C KB Q B 6 SW 2 Q C 7 C LR Q D BCD TO 7 SEGMENT DISPLAY 74LS390 U 1B 15 13 12 C KA Q A 11 C KB Q B 10 SW 14 Q C 9 C LR Q D BCD TO 7 SEGMENT DISPLAY 74LS390 Figure 6: Counter having M=100  Observe and explain the results ............................................................................................................................................. ............................................................................................................................................. b. Wire the 74LS390 as a MOD-60 counter  Use only an extra IC 74LS00 for wiring a counter having M = 60  Draw the circuit appropriately in figure 7. Figure 7 – Mod-60 counter  Show the way to implement: ................................................................................................................ ...................................................................................................................................... ...................................................................................................................................... ...................................................................................................................................... .... 4. PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER 74LS193 The counter IC 74LS193 has: • Data inputs: P3P2P1P0 • Count up pin: CLKU (CPU) • Count down pin:CLKD(CPD) • Load pin: LOAD ( PL ) • Data output :Q3Q2Q1Q0 • Clear pin: CLR (MR) DIGITAL LOGIC SYSTEMS Page 6 of 10
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE) • Carry pin: CO ( TCU ) • Borrow pin: BO ( TC D ) Figure 8: 74LS193 a. The function of each input and output  The outputs QA, QB, QC, QD and CO , BO are connected to Led display as figure 9.  The inputs are connected to switches. Set P3P2P1P0 are equal to 0000  1Hz clock is used for COUNT UP (CLKU) and COUNT DOWN (CLKD) 74LS193 SW0 15 P 0 U 1 Q 0 3 SW1 1 P 1 Q 1 2 SW2 10 P 2 Q 2 6 SW3 9 P 3 Q 3 7 4 13 5 C LKD BO 12 C LKU C O SW4 14 C LR SW5 11 LO AD 0 Figure 9 – 74LS193 Logic and connection diagram Check the following functions (fulfill the Table 1): CLR LOAD UP DOWN FUNCTION 0 1 CLK 1 0 1 1 CLK 0 1→0 X X 0→1 1 X X 0 1 1 1 Table 1  Let the circuit count up and down. What is the output state of CO and BO ? .............................................................................................................................................  What is the function of CO and BO ? ............................................................................................................................................. ............................................................................................................................................. b. Programmable up counters  Design a counter count up from 0100 to 1111 Show the way to implement: ............................................................................................................................................. DIGITAL LOGIC SYSTEMS Page 7 of 10
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE) ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. Draw the logic diagram in figure 10: Figure 10 - Counter count up from 0100 to 1111  Counter count up from 0000 to 1100 Show the way to implement: ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. Draw the logic diagram in figure 11: Figure 11 - Counter count up from 0000 to 1100  Counter count up from 0100 to 1101 Show the way to implement: ............................................................................................................................................. ............................................................................................................................................. DIGITAL LOGIC SYSTEMS Page 8 of 10
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE) ............................................................................................................................................. ............................................................................................................................................. Draw the logic diagram in figure 12: Figure 12 - Counter count up from 0100 to 1101 c. Programmable down counters  Design a counter count down from 1111 to 0100 Show the way to implement: ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. Draw the logic diagram in figure 13: Figure 13 - Counter count down from 1111 to 0100  Counter count down from 1101 to 0000 Show the way to implement: ............................................................................................................................................. ............................................................................................................................................. DIGITAL LOGIC SYSTEMS Page 9 of 10
INTERNATIONAL UNIVERSITY SCHOOL OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING (EE) ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. Draw the logic diagram in figure 14: Figure 14 - Counter count down from 1101 to 0000  Counter count down from 1101 to 0100 Show the way to implement: ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. ............................................................................................................................................. Draw the logic diagram in figure 15: Figure 15 - Counter count down from 1101 to 0100 ********* DIGITAL LOGIC SYSTEMS Page 10 of 10