VHDL for Efficient Testbenches
90
lượt xem 13
download
lượt xem 13
download
Download
Vui lòng tải xuống để xem tài liệu đầy đủ
Various efficient VHDL behavioural modelling language constructs are available to generate stimulus to test a VHDL model, e.g., • for loop • defining stimulus array & indexing the array to apply stimulus • reading stimulus data directly from a file Messages can also be added to testbench Remember that this type of testbench / behavioural VHDL code is not intended for logic synthesis, and normally cannot be synthesised ! Refer to muxAndDecEx1 lab files muxAndDecEx1_TB.vhd for these examples of testbench coding...
Chủ đề:
Bình luận(0) Đăng nhập để gửi bình luận!
CÓ THỂ BẠN MUỐN DOWNLOAD