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Chương 7 - Bộ nhớ

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256 MB dual in-line memory module organized for a 64-bit word with 16 16M × 8-bit RAM chips (eight chips on each side of the DIMM).

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Chapter 7 - Memory 7-1 Computer Architecture and Organization Miles Murdocca and Vincent Heuring Chapter 7 – Memory © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-2 Chapter Contents 7.1 The Memory Hierarchy 7.2 Random-Access Memory 7.3 Memory Chip Organization 7.4 Case Study: Rambus Memory 7.5 Cache Memory 7.6 Virtual Memory 7.7 Advanced Topics 7.8 Case Study: Associative Memory in Routers 7.9 Case Study: The Intel Pentium 4 Memory System © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-3 The Memory Hierarchy © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-4 Functional Behavior of a RAM Cell Static RAM cell (a) and dynamic RAM cell (b). © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-5 Simplified RAM Chip Pinout © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-6 A Four-Word Memory with Four Bits per Word in a 2D Organization © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-7 A Simplified Representation of the Four-Word by Four-Bit RAM © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-8 2-1/2D Organization of a 64-Word by One-Bit RAM © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-9 Two Four-Word by Four-Bit RAMs are Used in Creating a Four-Word by Eight- Bit RAM © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-10 Two Four-Word by Four-Bit RAMs Make up an Eight-Word by Four-Bit RAM © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-11 Single-In-Line Memory Module • 256 MB dual in-line memory module organized for a 64-bit word with 16 16M × 8-bit RAM chips (eight chips on each side of the DIMM). © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-12 Single-In- Line Memory Module • Schematic diagram of 256 MB dual in-line memory module. (Source: adapted from http://www- s.ti.com/sc/ds/tm4en64 kpu.pdf.) © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-13 A ROM Stores Four Four-Bit Words © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-14 A Lookup Table (LUT) Implements an Eight-Bit ALU © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-15 Flash Memory • (a) External view of flash memory module and (b) flash module internals. (Source: adapted from HowStuffWorks.com.) © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-16 Cell Structure for Flash Memory • Current flows from source to drain when a sufficient negative charge is placed on the dielectric material, preventing current flow through the word line. This is the logical 0 state. When the dielectric material is not charged, current flows between the bit and word lines, which is the logical 1 state. © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-17 Rambus Memory • Comparison of DRAM and RDRAM configurations. © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-18 Rambus Memory • Rambus technology on the Nintendo 64 motherboard (left) enables cost savings over the conventional Sega Saturn motherboard design (right). • Nintendo 64 game console: © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-19 Placement of Cache Memory in a Computer System • The locality principle: a recently referenced memory location is likely to be referenced again (temporal locality); a neighbor of a recently referenced memory location is likely to be referenced (spatial locality). © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring
Chapter 7 - Memory 7-20 An Associative Mapping Scheme for a Cache Memory © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization by M. Murdocca and V. Heuring

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