NguyÔn ViÕt TuyÕn XLTT TT 2003–
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Lêi cam ®oan
T«i xin cam ®oan b¶n luËn v¨n nµy lµ kÕt qu¶ nghiªn cøu cña b¶n th©n
díi sù híng dÉn cña TS. §Æng V¨n ChuyÕt. NÕu cã g× sai ph¹m, t«i xin chÞu
hoµn toµn tr¸ch nhiÖm.
Ngêi lµm cam ®oan
NguyÔn ViÕt TuyÕn
NguyÔn ViÕt TuyÕn XLTT TT 2003–
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Môc lôc
Trang
Lêi cam ®oan.............................................................................................. 1
Môc lôc ......................................................................................................... 2
Danh môc c¸c ký hiÖu, c¸c ch÷ viÕt t¾t .................................... 5
Danh môc c¸c h×nh vÏ .......................................................................... 6
Lêi nãi ®Çu .................................................................................................. 7
Ch¬ng 1:Tæng quan vÒ m¹ch logic lËp tr×nh ®îc ............... 9
1.1. LÞCH Sö PH¸T TRIÓN CñA VI M¹CH Sè LËP TR×NH . ................... 9
1.2. CÊu tróc cña thiÕt bÞ logic cã thÓ lËp tr×nh ®îc
(Programmable Logic Architecture: PLA) .............................. 12
1.3. Nh÷ng u thÕ cña thiÕt kÕ ®îc trî gióp cña m¸y
tÝnh vµ logic cã thÓ lËp tr×nh (Computer Aided Design -
and Programmable Logic) ............................................................... 15
1.4. D·y c¸c cæng logic lËp tr×nh ®îc theo trêng
(FPGA: Field Programmable Gate Array) ................................. 18
1.4.1. Giíi thiÖu ....................................................................................... 18
1.4.2. CÊu tróc cña FPGA. ....................................................................... 18
1.4.3. C¸c kªnh kÕt nèi ............................................................................ 28
1.4.4. M¹ng kÕt nèi tæng thÓ vµ c¸c bé ®Öm ........................................... 31
Ch¬ng 2: Ng«n ng÷ m« t¶ phÇn cøng VHDL (Very High
Speed Intergrated Circuit Hardware Description
Language) ................................................................................................. 33
2.1. Më ®Çu .................................................................................................. 33
2.1.1. Giíi thiÖu ....................................................................................... 33
2.1.2 C¸c thuËt ng÷ cña VHDL ............................................................... 36
2.2. CÊu tróc cña mét ch¬ng tr×nh VHDL ............................... 37
2.3. C¸c ®¬n vÞ thiÕt kÕ trong VHDL ............................................. 38
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2.3.1.Gãi (Package) ................................................................................. 38
2.3.2. Thùc thÓ (Entity) ........................................................................... 40
2.3.3.KiÕn tróc (Architecture) ................................................................. 40
2.3.4.CÊu h×nh (Configuration) ...............................................................42
2.4. C¸c kiÓu d÷ liÖu trong VHDL ................................................... 43
2.4.1. C¸c ®èi tîng d÷ liÖu..................................................................... 43
2.4.2. C¸c kiÓu d÷ liÖu ............................................................................. 45
2.5. To¸n tö vµ biÓu thøc .................................................................... 45
2.5.1. C¸c to¸n tö. .................................................................................... 46
2.5.2. C¸c to¸n h¹ng ................................................................................ 46
2.6. C¸c lÖnh tuÇn tù trong VHDL ................................................. 47
2.6.1.C©u lÖnh g¸n biÕn. .......................................................................... 47
2.6.2.C©u lÖnh g¸n tÝn hiÖu. ..................................................................... 47
2.6.3. C©u lÖnh if ..................................................................................... 48
2.6.4. C©u lÖnh Case ................................................................................ 48
2.6.5. C¸c lÖnh vßng lÆp .......................................................................... 49
2.6.6. C©u lÖnh Null ................................................................................. 50
2.7. C¸c lÖnh song song trong VHDL ........................................... 51
2.7.1. C¸c qu¸ tr×nh Process. ................................................................... 51
2.7.2. C¸c phÐp g¸n tÝn hiÖu song song ................................................... 52
2.7.3. PhÐp g¸n tÝn hiÖu cã ®iÒu kiÖn ...................................................... 53
2.7.4. PhÐp g¸n theo lùa chän .................................................................. 55
2.7.5. Khèi ............................................................................................... 56
2.7.6. Gäi ch¬ng tr×nh con song song .................................................... 57
2.7. Ch¬ng tr×nh con .......................................................................... 58
Ch¬ng 3: ThiÕt kÕ modul Thùc hµnh FPGA sö dông FPGA
XC2S100 5PQ144C cña Xilinx- ................................................................ 60
3.1. Tr×nh tù thiÕt kÕ víi FPGA ......................................................... 60
3.2. ThiÕt kÕ modul thùc hµnh FPGA ............................................ 61
3.2.1. Môc ®Ých vµ yªu cÇu cña modul .................................................... 61
3.2.2. S¬ ®å khèi vµ ®Æc ®iÓm cña c¸c khèi ............................................ 62
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3.2.3. Nh÷ng c«ng cô sö dông khi thiÕt kÕ modul. ................................64
3.2.4. ThiÕt kÕ c¸c khèi chøc n¨ng cña modul ........................................ 65
3.3.ThiÕt kÕ mÉu m¹ch gi¶i m· bµn phÝm ch¹y thö trªn
modul. ......................................................................................................... 73
3.3.1. ThiÕt kÕ ch¬ng tr×nh VHDL ........................................................ 74
3.3.2.Tæng hîp thiÕt kÕ ............................................................................ 89
3.3.3. §Æt ch©n cho FPGA ....................................................................... 90
3.3.4.T¹o chuçi bit ................................................................................... 90
3.3.5. N¹p FPGA vµ ch¹y thö .................................................................. 91
KÕt luËn ..................................................................................................... 92
Tµi liÖu tham kh¶o ............................................................................... 93
Phô lôc 1: Ch¬ng tr×nh nguån khèi t¹o tÝn hiÖu ®Çu vµo
Phô lôc 2: Ch¬ng tr×nh VHDL m« t¶ bé ®Õm
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Danh môc c¸c ký hiÖu, c¸c ch÷ viÕt t¾t
Ký hiÖu viÕt t¾t
0BTiÕng Anh
IFL
Intergrated Fuse Logic
MSI
Medium Scale Integrated
PCB
Printed Circuit Board
AMD
Advance Micro Devices
ASIC
Application Specific Integrated Circuit
AMAZE
Automated Map and Zap Equations
CPLD
Complex Programmable Logic Devices
CPLD
Complex Programmable Logic Devices
CAD
Computer Aided Design
CLBs
Configurable Logic Blocks
ERASIC
Erasable Application Specific IC
FPGA
Field Programmable Gate Array
GAL
Generic Array Logic
GSR
Global Initialization Signal
HDL
Hardware Description Languages
IOBs
Input/Output Blocks
LCA
Logic Call Array
PAL
Programmable Array Logic
PLA
Programmable Logic Device
PML
Programmable Macro Logic
SPLD
Simple Programmable Logic Devices
SSI
Small Scale Integrated
CUPL
Universal Compiler for Programmable
VHDL
Very High Speed Intergra
ted Circuit
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