intTypePromotion=1
zunia.vn Tuyển sinh 2024 dành cho Gen-Z zunia.vn zunia.vn
ADSENSE
 » 
 » 

Bài giảng Xử lý tin hiệu số với FPGA: Chương 1 - Hoàng Trang

Chia sẻ: _ _ | Ngày: | Loại File: PDF | Số trang:55

Thêm vào BST
Báo xấu
6
lượt xem 2
download
 
  Download Vui lòng tải xuống để xem tài liệu đầy đủ

Bài giảng "Xử lý tin hiệu số với FPGA" Chương 1: Tổng quan, cung cấp cho người học những kiến thức như: tổng quan môn học; phương pháp luận thiết kế và giải pháp FPGA; thiết kế giải thuật DSP với FPGA. Mời các bạn cùng tham khảo!

Chủ đề:

Bình luận(0) Đăng nhập để gửi bình luận!

Lưu

Nội dung Text: Bài giảng Xử lý tin hiệu số với FPGA: Chương 1 - Hoàng Trang

  1. 1/26/2013 Đ I H C QU C GIA TP.H CHÍ MINH TRƯ NG Đ I H C BÁCH KHOA KHOA ĐI N-ĐI N T B MÔN K THU T ĐI N T X LÝ TÍN Hi U S V I FPGA Chaper 1: Introduction om GV: Hoàng Trang .c Email: hoangtrang@hcmut.edu.vn mr.hoangtrang@gmail.com ng Thank to: th y H Trung M co TP.H Chí Minh 01/2013 1 an th ng Content o du + T ng quan môn h c u cu + Phương pháp lu n thi t k và gi i pháp FPGA + Thi t k gi i thu t DSP v i FPGA BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 2 1 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  2. 1/26/2013 Outline: how to evaluate? How to evaluate? 1. Quiz: 10% 2. Homework (textbook) : 10% (team work) 3. Project: 20% (team work) 4. Mid-term: 20% om 5. Final exam: 40% .c Textbook: “VLSI Digital Signal Processing: Design and Implementation” ng Keshab K. Parhi co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 3 an th ng Outline o du Hardware Algorithm design and • DSP Systems, A/D and D/A transformations converters • Scheduling, Resource u • FPGA for signal processing Allocation, Synthesis cu (Altera, Xilinx), • Finite-word length effects • Application domain specific • Algorithmic transformations instruction set processors • FIR filter design • SoC, DSP Multiprocessors • FFT design • Signal processing arithmetic • IIR filter design units • Adaptive filter design BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 4 2 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  3. 1/26/2013 Course Conduct • Course notes will be posted on the course web page • Assignments with solutions will be provided and will not be graded • The exam will be prepared based on lecture om slides, references and assignments .c ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 5 an th ng Course Objectives … To o du • Understand tradeoffs in implementing DSP algorithms u • Know basic DSP architectures cu • Know some reduced complexity strategies for algorithms mainly on FPGA. • Know about commercial DSP solution • Know and understand system-level design tools • Understand research topics related to algorithmic modifications and algorithm-architecture matching BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 6 3 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  4. 1/26/2013 Why this course? There is the demand to derive more information per signal. “More” means • Faster: Derive more information per unit time; – Faster hardware – Newer algorithms with fewer operations om • Cheaper: Derive information at a reduced cost in processor size, weight, power consumption, or .c dollars; • Better: Derive higher quality information, (higher ng precision, finer resolution, higher SNR) co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 7 an th ng Hardware and software elements o Progress in signal processing capability is the product of du progress in IC devices, architectures, algorithms and mathematics. u cu BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 8 4 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  5. 1/26/2013 Moore’s Law Predicts doubling of circuit density every 1.5 to 2 years. om .c ng http://www.icknowledge.com/trends/uproc.html co 9 BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 9 an th ng What is Signal Processing? o du • Ways to manipulate signal • Types of processing: – Transformation in its original medium or an – Filtering u abstract representation. – Detection cu • Signal can be abstracted as – Estimation functions of time or spatial – Recognition and classification coordinates. – Coding (compression) – Synthesis and reproduction – Recording, archiving – Analyzing, modeling 10 BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 10 5 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  6. 1/26/2013 Digital Signal Processing • Signals generated via • Digital signal processing physical phenomenon are concerns processing signals analog in that using digital computers. – Their amplitudes are defined – A continuous time/space over the range of signal must be sampled to real/complex numbers yield countable signal om – Their domains are continuous samples. in time or space. – The real-(complex) valued samples must be quantized to .c fit into internal word length. ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 11 an th ng Digital Signal Processing applications o du u cu BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 12 6 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  7. 1/26/2013 Signal Processing Systems Digital Signal D/A A/D Processing The task of digital signal processing (DSP) is to process om sampled signals (from A/D analog to digital converter), and provide its output to the D/A (digital to analog converter) to .c be transformed back to physical signals. ng co Copied from [Hu04-Slides] Design and Implementation of Signal Processing Systems: An Introduction BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 13 an th ng Typical DSP Application o du u cu BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 14 7 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  8. 1/26/2013 Stratix DSP Development Board Nios Expansion MAX 7000 Device Prototype Connector Prototyping Area D/A Converters Mictor-Type Connectors for HP Logic Analyzers A/D Converters om .c Analog SMA Connectors ng 40-Pin Connectors Texas Instruments Connectors on for Analog Devices Underside of Board co [AlteraDSP] BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 15 an th ng Example DSP Applications…. o du COMMUNICATIONS VOICE/SPEECH PRO- PRO-AUDIO Echo Cancellation Speech Recognition AV Editing Digital PBXs Speech Processing/Vocoding Digital Mixers u Line Repeaters Speech Enhancement Home Theater Modems Text-to-Speech Pro Audio Global Positioning Voice Mail cu Sound/Modem/Fax Cards Cellular Phones Speaker Phones CONSUMER Video Conferencing Radar Detectors ATMs Power Tools Digital Audio / TV DSP Music Synthesizers Toys / Games INSTRUMENTATION Answering Machines Spectrum Analyzers Digital Speakers Seismic Processors Digital Oscilloscopes Mass Spectrometers MILITARY INDUSTRIAL/CONTROL MEDICAL Secure Communications Patient Monitoring Robotics Sonar Processing Ultrasound Equipment Numeric Control Image Processing Diagnostic Tools Power Line Monitors Radar Processing Fetal Monitors Motor/Servo Control Navigation, Guidance Life Support Systems Image Enhancement www.analog.com/dsp BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 16 8 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  9. 1/26/2013 Implementation of DSP Systems • Platforms: • Requirements: – Native signal processing (NSP) – Real time with general purpose processors • Processing must be done (GPP) before a pre-specified • Multimedia extension (MMX) deadline. instructions – Streamed numerical data – Programmable digital signal • Sequential processing processors (PDSP) om • Fast arithmetic processing – Application-Specific Integrated – High throughput Circuits (ASIC) • Fast data input/output .c – Field-programmable gate array • Fast manipulation of data (FPGA) ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 17 an th ng How Fast is Enough for DSP? o • Different throughput rates for du • Real time requirements: processing different signals – Example: data capture speed must match sampling rate. Otherwise, – Throughput ∝sampling rate. u data will be lost. – CD music: 44.1 kHz cu – Processing must be done by a – Speech: 8-22 kHz specific deadline. – Video (depends on frame rate, frame size, etc.) range from 100s kHz to MHz. Example: Processor clocked at 120 MHz and can perform 120MIPS + Sampling rate = 48KHz (Digital Audio Tape - DAT) number of instructions per sample = (120 x 106)/(48 x 103) = 2500. + Sampling rate = 8KHz (voice-band, telephony) number of instructions per sample = 15000. + Sampling rate = 75MHz (CIF 360x288 Video at 30 frames per second) number of instructions per sample = 1.6. BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 18 9 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  10. 1/26/2013 ASIC: Application Specific ICs • Custom or semi-custom IC chip or • ASIC becomes popular due to chip sets developed for specific availability of IC foundry functions. services. Fab-less design houses turn innovative design • Suitable for high volume, low cost into profitable chip sets using productions. CAD tools. • Example: MPEG codec, 3D graphic • Design automation is a key om chip, etc. enabling technology to facilitate fast design cycle and shorter time to market delay. .c ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 19 an th ng Programmable Digital Signal Processors (PDSPs) o du • Micro-processors designed for • PDSPs were developed to fill a signal processing applications. market segment between GPP u and ASIC: cu • Special hardware support for: – Multiply-and-Accumulate (MAC) ops – GPP flexible, but slow – Saturation arithmetic ops – ASIC fast, but inflexible – Zero-overhead loop ops • As VLSI technology improves, – Dedicated data I/O ports role of PDSP changed over – Complex address calculation and time. memory access – Cost: design, sales, – Real time clock and other embedded maintenance/upgrade processing supports. – Performance BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 20 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  11. 1/26/2013 Programmable Digital Signal Processors (PDSPs) example om .c ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 21 an th ng PDSP Market – By Company o du 2001 Market Share 2002 Market Share u 24% cu 20% Texas Instruments 40% Motorola Agere 43% 8% Analog Devices 9% Other 16% 12% 14% 14% Ref: Forward Concepts http://www.fwdconcepts.com/Pages/press42.htm BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 22 11 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  12. 1/26/2013 DSP Market – By Application Market Share - 2003 4% 3% 6% 8% WIRELESS CONSUMER MULTIPURPOSE 11% WIRELINE om COMPUTER 68% AUTOMOTIVE .c Ref: Forward Concepts ng http://www.fwdconcepts.com/Pages/press42.htm co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 23 an th ng Computing using FPGA o du • FPGA (Field programmable gate array) is a • Use of FPGA derivative of PLD (programmable logic – Rapid prototyping: run fractional u devices). ASIC speed without fab delay. cu • They are hardware configurable to behave – Hardware accelerator: using the differently for different configurations. same hardware to realize • Slower than ASIC, but faster than PDSP. different function modules to • Once configured, it behaves like an ASIC save hardware module. – Low quantity system deployment BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 24 12 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  13. 1/26/2013 FPGA example: Stratix EP1S10 om .c ng Altera Corp., Stratix Module 2: Logic Structure & MultiTrack Interconnect, 2004. co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 25 an th ng IP Cores o du • Processor cores Start-Core – 16-bit fixed-point VLIW DSP core from Lucent/Motorola (a company is u established by Lucent for DSP section called “Agere”) cu – First VLIW machine to target low-power applications – Pipeline relatively simple – Targeting 198 mW @ 300 MHz, 1.5 V • Hardware cores Altera DSP coresDevice Type – FIR Compiler – IIR Compiler – FFT/IFFT Compiler Transforms – NCO Compiler Signal Generation – Reed-Solomon Compiler Error Detection / Correction – Constellation Mapper/Demapper Modulation / Demodulation – Viterbi Compiler Error Detection / Correction BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 26 13 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  14. 1/26/2013 SoC (System-on-Chip) • With the continuing scaling of modern IC • SoC uses intellectual properties (IPs) devices, it is now possible to incorporate that are pre-designed modules. – Micro-processor cores + ASIC function • Designing SoC thus becomes a task blocks of system integration. – Analog + digital components – Computation + communication functions • Challenge issues in SoC design: – I/O, memory + processor – Interface among IPs from different into the same chip to form a venders om comprehensive “system”. – Verification of function Thus, the notion of System-on-chip (SoC) – Physical design challenges .c ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 27 an th ng Design Issues????!!!! o du • Software design: • Given a DSP application, which – NSP, PDSP implementation option should be – Algorithms are implemented as u chosen? programs. cu • For a particular implementation • Hardware design: option, how to achieve optimal – ASIC, FPGA design? Optimal in terms of what – Algorithms are directly implemented in hardware criteria? modules. • S/H Co-design: System level design methodology. A design methodology is the overall strategy to organize and solve the design tasks at the different steps of the design process Design methodology is viewed as the development of a sequence of models of the system, where each version is more refined than the previous one BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 28 14 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  15. 1/26/2013 Design Process Model • Design is the process that links • Implementation algorithm to implementation – Assignment: Each • Algorithm operation can be realized with – Operations • One or more instructions – Dependency between operations (software) determines a partial ordering of • One or more function om execution modules (hardware) – Can be specified as a dependence – Scheduling: Dependence relations and resource .c graph constraints leads to a schedule. ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 29 an th ng A Design Example … o du Consider the algorithm: • Operations: n – Multiplication u y = ∑ a ( k ) x( k ) – Addition cu k =1 • Dependency – y(k) depends on y(k-1) Program: – Dependence Graph: y(0) = 0 For k = 1 to n Do a(1) x(1) a(2) x(2) a(n) x(n) y(k) = y(k-1)+ a(k)*x(k) End * * * y = y(n) y(0) + + + y(n) BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 30 15 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  16. 1/26/2013 Design Example cont’d … • Software Implementation: • Hardware Implementation: – Map each * op. to a MUL instruction, – Map each * op. to a multiplier, and each + op. to a ADD instruction. and each + op. to an adder. – Allocate memory space for {a(k)}, {x(k)}, and {y(k)} – Interconnect them according – Schedule the operation by sequentially to the dependence graph: execute y(1)=a(1)*x(1), y(2)=y(1) + a(2)*x(2), etc. om – Note that each instruction is still to be implemented in hardware. a(1) x(1) a(2) x(2) a(n) x(n) .c * * * y(0) + + + y(n) ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 31 an th ng Observations o du • Eventually, an implementation is • Bottom line – Hardware/ realized with hardware. software co-design. There is a continuation between u • However, by using the same hardware and software cu hardware to realize different implementation. operations at different time • A design must explore both (scheduling), we have a simultaneously to achieve software program! best performance/cost trade- off. BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 32 16 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  17. 1/26/2013 A Theme • Matching hardware to algorithm • Formulate algorithm to match – Hardware architecture must match hardware the characteristics of the algorithm. – Algorithm must be formulated so – Example: ASIC architecture is that they can best exploit the designed to implement a specific potential of architecture. algorithm, and hence can achieve – Example: GPP, PDSP architectures superior performance. are fixed. One must formulate the om algorithm properly to achieve best performance. Eg. To minimize number of operations. .c ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 33 an th ng Algorithm Reformulation o du • Algorithmic level equivalence u – Different filter structures implementing the same cu specification • Exploiting parallelism – Regular iterative algorithms and loop reformulation • Well studied in parallel compiler technology – Signal flow/Data flow representation • Suitable for specification of pipelining BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 34 17 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  18. 1/26/2013 Mapping Algorithm to Architecture • Scheduling and Assignment Problem – Resources: hardware modules, and time slots – Demands: operations (algorithm), and throughput • Constrained optimization problem – Minimize resources (objective function) to meet om demands (constraints) .c • For regular iterative algorithms and regular processor arrays -> algebraic mapping. ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 35 an th ng Implementation process for PDSP o du u cu BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 36 18 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  19. 1/26/2013 Direct Mapping Techniques om .c ng co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 37 an th ng FIR Filters o du u cu BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 38 19 CuuDuongThanCong.com https://fb.com/tailieudientucntt
  20. 1/26/2013 Transposed FIR Filter om Algorithm transform techniques: – Pipelining and parallelism (Parallelism parallel FIR filter: 3 inputs .c are processed at the same time to produce 3 outputs) – Retiming (Retiming is a transformation technique used to change ng location of delay elements: reducing the clock period, reducing the number of registers) – Unfolding-loop unrolling co BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 39 an th ng Example: One-to-one mapping and pipelining o du A B C D u allocation A B C D cu assignment A B C D Analyse timing pipelining A B C D • if OK then stop • else pipelining clocked flip-flop ≡ ff clock BM Đi n T -DSP-FPGA-chapter1 Hoàng Trang 01/2013 40 20 CuuDuongThanCong.com https://fb.com/tailieudientucntt
ADSENSE

CÓ THỂ BẠN MUỐN DOWNLOAD

LV.15: Bộ Đồ Án Tốt Nghiệp Chuyên Ngành Cơ Khí
65 tài liệu
2431 lượt tải
THÔNG TIN
TRỢ GIÚP
HỖ TRỢ KHÁCH HÀNG
Theo dõi chúng tôi

Chịu trách nhiệm nội dung:

Nguyễn Công Hà - Giám đốc Công ty TNHH TÀI LIỆU TRỰC TUYẾN VI NA

LIÊN HỆ

Địa chỉ: P402, 54A Nơ Trang Long, Phường 14, Q.Bình Thạnh, TP.HCM

Hotline: 093 303 0098

Email: support@tailieu.vn

Giấy phép Mạng Xã Hội số: 670/GP-BTTTT cấp ngày 30/11/2015 Copyright © 2022-2032 TaiLieu.VN. All rights reserved.

 

Đồng bộ tài khoản
2=>2